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參數(shù)資料
| 型號： | HI5804 |
| 廠商： | Intersil Corporation |
| 英文描述： | 12-Bit, 5 MSPS A/D Converter |
| 中文描述： | 12位，5 MSPS的A / D轉(zhuǎn)換 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大?。?/td> | 64K |
| 代理商： | HI5804 |
10
HI5804
Spurious Free Dynamic Range (SFDR)
SFDR is the ratio of the fundamental RMS amplitude to the
RMS amplitude of the next largest spur or spectral
component in the spectrum below f
S
/2.
Transient Response
Transient response is measured by providing a full scale
transition to the analog input of the ADC and measuring the
number of cycles it takes for the output code to settle within
12-bit accuracy.
Overvoltage Recovery
Overvoltage Recovery is measured by providing a full scale
transition to the analog input of the ADC which overdrives
the input by 200mV, and measuring the number of cycles it
takes for the output code to settle within 12-bit accuracy.
Full Power Input Bandwidth (FPBW)
Full power input bandwidth is the frequency at which the
amplitude of the digitally reconstructed output has
decreased 3dB below the amplitude of the input sine wave.
The input sine wave has a peak-to-peak amplitude equal to
the difference between the two internal voltage references.
The bandwidth given is measured at the specified sampling
frequency.
Timing Definitions
Refer to Figure 1 and Figure 2 for these definitions.
Aperture Delay (t
AP
)
Aperture delay is the time delay between the external sam-
ple command (the falling edge of the clock) and the time at
which the signal is actually sampled. This delay is due to
internal clock path propagation delays.
Aperture Jitter (t
AJ
)
Aperture Jitter is the RMS variation in the aperture delay due
to variation of internal clock path delays.
Data Hold Time (t
H
)
Data hold time is the time to where the previous data (N - 1)
is no longer valid.
Data Output Delay Time (t
OD
)
Data output delay time is the time to where the new data (N)
is valid.
Data Latency (t
LAT
)
After the analog sample is taken, the digital data is output on
the bus after the third cycle of the clock. This is due to the
pipeline nature of the converter where the data has to ripple
through the stages. This delay is specified as the data latency.
After the data latency time, the data representing each
succeeding sample is output at the following clock pulse. The
digital data lags the analog input sample by 3 clock cycles.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HI5804EVAL | 12-Bit, 5 MSPS A/D Converter |
| HI5804KCB | 12-Bit, 5 MSPS A/D Converter |
| HI5812JIB | CMOS 20 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold |
| HI5812JIJ | CMOS 20 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold |
| HI5812JIP | CMOS 20 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI5804EVAL | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| hi5804kcb | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| HI5805 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:12-Bit, 5MSPS A/D Converter |
| HI5805_05 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:12-Bit, 5MSPS A/D Converter |
| HI5805BIB | 功能描述:IC ADC 12-BIT 5MSPS 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
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