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參數(shù)資料
| 型號： | HIP1020CK-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 6/6頁 |
| 文件大小： | 331K |
| 描述： | IC CTRLR HOT PLUG SOT23-5 |
| 標準包裝： | 3,000 |
| 類型： | 熱交換控制器 |
| 應用： | 通用 |
| 內部開關： | 無 |
| 電源電壓： | 5V，12V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SC-74A，SOT-753 |
| 供應商設備封裝： | SOT-23-5 |
| 包裝： | 帶卷 (TR) |
6
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli-
able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Special Applications
The HIP1020 is well suited to work with N-Channel
MOSFETs controlling voltages other than 12V, 5V, or 3.3V
provided three basic constraints are observed. The first
constraint is that the bias voltage for the HIP1020 is either
12V or 5V. Chip operation at voltages significantly below 5V
is not possible, while a bias voltage very much above 12V
can unnecessarily stress the part. Operation between 5V
and 12V can confuse the chip as it tries to determine
whether to operate as a voltage doubler or voltage tripler.
The final two constraints have to do with proper operation of
the power MOSFETs. These constraints assume that a rail
voltage, V
RAIL
, is to be switched using an N-Channel power
MOSFET having a gate-to-source breakdown voltage of V
BR
and a threshold voltage of V
TH
.
V
GATE
can be either V
HGATE
or V
LGATE
depending on
which pin is connected to the power MOSFET and will be
selected based on which gate voltage is most appropriate for
the application. The requirement in Equation 2 is necessary
to assure that the power MOSFET is fully enhanced. V
TH
should be the maximum data-sheet value needed to assure
adequately low r
DSON
. The requirement in Equation 3
assures that the power MOSFET is protected from
breakdown of the gate oxide.
V
TH
V
GATE
V
RAIL
<
(EQ. 2)
V
BR
V
GATE
V
RAIL
>
(EQ. 3)
HIP1020
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