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參數資料
| 型號： | HIP6017B |
| 廠商： | Intersil Corporation |
| 元件分類： | FPGA |
| 英文描述： | FPGA - 100000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 先進的雙PWM和線性功率控制 |
| 文件頁數： | 13/16頁 |
| 文件大小： | 139K |
| 代理商： | HIP6017B |
13
supply the RMS current. Small ceramic capacitors should be
placed very close to the upper MOSFET to suppress the
voltage induced in the parasitic circuit impedances.
For a through hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo
MV-GX or equivalent) may be needed. For surface mount
designs, solid tantalum capacitors can be used, but caution
must be exercised with regard to the capacitor surge current
rating. These capacitors must be capable of handling the
surge-current at power-up. The TPS series available from
AVX, and the 593D series from Sprague are both surge
current tested.
Transistor Selection/Considerations
The HIP6017B requires 3 external transistors. Two
N-Channel MOSFETs are used in the synchronous-rectified
buck topology of the PWM converter. The linear controller
drives either a MOSFET or a NPN bipolar as a pass
transistor. These transistors should be selected based upon
r
DS(ON)
, gate supply requirements, and thermal
management requirements.
PWM1 MOSFET Selection and Considerations
In high-current PWM applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors. The power dissipation includes
two loss components; conduction loss and switching loss.
These losses are distributed between the upper and lower
MOSFETs according to duty factor (see the equations
below). The conduction loss is the only component of
power dissipation for the lower MOSFET. Only the upper
MOSFET has switching losses, since the lower device
turns on into near zero voltage.
The equations below assume linear voltage-current
transitions and do not model power loss due to the reverse-
recovery of the lower MOSFET’s body diode. The gate-
charge losses are proportional to the switching frequency
(F
S
) and are dissipated by the HIP6017B, thus not
contributing to the MOSFETs’ temperature rise. However,
large gate charge increases the switching interval, t
SW
which increases the upper MOSFET switching losses.
Ensure that both MOSFETs are within their maximum
junction temperature at high ambient temperature by
calculating the temperature rise according to package
thermal resistance specifications. A separate heatsink may
be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
The r
DS(ON)
is different for the two previous equations even
if the type device is used for both. This is because the gate
drive applied to the upper MOSFET is different than the
lower MOSFET. Figure 14 shows the gate drive where the
upper gate-to-source voltage is approximately V
CC
less the
input supply. For +5V main power and +12VDC for the bias,
the gate-to-source voltage of Q1 is 7V. The lower gate drive
voltage is +12VDC. A logic-level MOSFET is a good choice
for Q1 and a logic-level MOSFET can be used for Q2 if its
absolute gate-to-source voltage rating exceeds the
maximum voltage applied to V
CC
.
Rectifier CR1 is a clamp that catches the negative inductor
voltage swing during the dead time between the turn off of
the lower MOSFET and the turn on of the upper MOSFET.
The diode must be a Schottky type to prevent the lossy
parasitic MOSFET body diode from conducting. It is
acceptable to omit the diode and let the body diode of the
lower MOSFET clamp the negative inductor swing, but
efficiency might drop one or two percent as a result. The
diode's rated reverse breakdown voltage must be greater
than twice the maximum input voltage.
Linear Controller Transistor Selection
The main criteria for selection of transistors for the linear
regulators is package selection for efficient removal of heat.
The power dissipated in a linear regulator is:
Select a package and heatsink that maintains the junction
temperature below the maximum rating while operating at
the highest expected ambient temperature.
When selecting bipolar NPN transistors for use with the
linear controllers, insure the current gain at the given
operating VCE is sufficiently large to provide the desired
output load current when the base is fed with the minimum
driver output current.
P
UPPER
I
------------------------------------------------------------
2
r
IN
×
V
×
I
----------------------------------------------------
V
×
t
×
F
S
×
+
=
P
LOWER
I
---------------------------------------------------------------------------------
2
r
IN
×
V
V
–
(
)
×
=
+12V
PGND
HIP6017B
GND
LGATE
UGATE
PHASE
V
CC
+5V OR LESS
NOTE:
V
GS
≈
V
CC
-5V
NOTE:
V
GS
≈
V
CC
Q1
Q2
+
-
FIGURE 14. OUTPUT GATE DRIVERS
CR1
P
LINEAR
I
O
V
IN
V
OUT
–
(
)
×
=
HIP6017B
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|---|---|
| HIP6017BCB | FPGA - 100000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| HIP6017BCB | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Advanced PWM and Dual Linear Power Control |
| HIP6017BCB WAF | 制造商:Harris Corporation 功能描述: |
| HIP6017BCB-T | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| HIP6017CB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HIP6017CB WAF | 制造商:Harris Corporation 功能描述: |
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