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參數(shù)資料
型號: HIP6020
廠商: Intersil Corporation
元件分類: FPGA
英文描述: FPGA - 100000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN
中文描述: 先進(jìn)的雙PWM和線性雙電源控制器
文件頁數(shù): 11/15頁
文件大小: 139K
代理商: HIP6020
2-291
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
E/A
. This function is dominated by a DC
Gain, given by V
IN
/V
OSC
, and shaped by the output filter, with
a double pole break frequency at F
LC
and a zero at F
ESR
.
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the HIP6020) and the impedance networks Z
IN
and
Z
FB
. The goal of the compensation network is to provide a
closed loop transfer function with high 0dB crossing frequency
(f
0dB
) and adequate phase margin. Phase margin is the
difference between the closed loop phase at f
0dB
and 180
degrees
.
The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 11. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1
ST
Zero Below Filter’s Double Pole (~75% F
LC
)
3. Place 2
ND
Zero at Filter’s Double Pole
4. Place 1
ST
Pole at the ESR Zero
5. Place 2
ND
Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
Compensation Break Frequency Equations
Figure 12 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown in Figure 12. Using the above guidelines
should yield a Compensation Gain similar to the curve plotted.
The open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at F
P2
with the capabilities
of the error amplifier. The Closed Loop Gain is constructed on
the log-log graph of Figure 12 by adding the Modulator Gain (in
dB) to the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the compensation
transfer function and plotting the gain.
The compensation gain uses external impedance networks
Z
FB
and Z
IN
to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than
45 degrees. Include worst case component variations when
determining phase margin.
PWM2 Controller Feedback Compensation
To reduce the number of external small-signal components
required by a typical application, the standard PWM
controller is internally stabilized. The only stability criteria
that needs to be met relates the minimum value of the output
inductor to the equivalent ESR of the output capacitor bank,
as shown in the following equation:
FIGURE 8. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
V
OUT
OSC
REFERENCE
L
O
C
O
ESR
V
IN
V
OSC
ERROR
AMP
PWM
COMP
+
-
DRIVER
(PARASITIC)
Z
FB
+
-
DACOUT
R1
R3
R2
C3
C2
C1
COMP
V
OUT
FB
Z
FB
HIP6020
Z
IN
DRIVER
DETAILED COMPENSATION COMPONENTS
PHASE
V
E/A
+
-
Z
IN
F
LC
L
O
2
π
C
O
×
×
---------------------------------------
=
F
ESR
O
-----------------------------------------
=
F
Z1
-----------------------------------
=
F
Z2
R3
)
C3
×
------------------------+
=
F
P1
2
π
R
2
----------+
×
×
------------------------------------------------------
=
F
P2
-----------------------------------
=
100
80
60
40
20
0
-20
-40
-60
F
P1
F
Z2
10M
1M
100K
10K
1K
100
10
OPEN LOOP
ERROR AMP GAIN
F
Z1
F
P2
F
LC
F
ESR
COMPENSATION
GAIN
G
FREQUENCY (Hz)
MODULATOR
GAIN
FIGURE 9. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
CLOSED LOOP
GAIN
20
P
-----------------
log
20
-------
log
L
OUT MIN
)
ESR
10
1.75
×
------------------------------------------------
=
HIP6020
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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