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參數(shù)資料
| 型號(hào)： | HIP7020 |
| 廠商： | Intersil Corporation |
| 元件分類： | FPGA |
| 英文描述： | FPGA 2000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | J1850總線收發(fā)器，多重布線系統(tǒng) |
| 文件頁數(shù)： | 1/11頁 |
| 文件大小： | 81K |
| 代理商： | HIP7020 |
1
June 1998
HIP7020
J1850 Bus Transceiver
For Multiplex Wiring Systems
Features
J1850 Bus Transceiver for MX Wiring
5V CMOS/TTL Logic Interface
Current Controlled Transmitter Driver
Controlled Rise/Fall Time of Bus Drive for Both
Voltage and Current
Bus Drive Capability to Less Than 500
with a 5
μ
s
Load RC Time Constant
Filtered Bus Input Receiver
Ground Fault Tolerant for Bus Isolation
Short Circuit and Over Temperature Protection
Protection for Reverse Battery, Load Dump
and Latch-Up
±
9kV ESD Protection BUS OUT and BATTERY Pins
-40
o
C to 125
o
C Operating Range
Loop-Back Fault Detection Mode
4x (41.6kHz) Receive Speed
Description
The HIP7020 IC is an Integrated I/O Bus Transceiver
designed for the SAE Standard
J1850 Class B Data Com-
munication Network Interface
. The Bus transmits and
receives data on a single wire using a 10.4kHz VPWM (Vari-
able Pulse Width Modulated) signal. The HIP7020 serves as
an I/O buffer interfacing to 5V CMOS logic. It is designed to
operate directly from the 12V battery line of an automobile.
The normal Bus voltage swing capability is from 0V to 7.75V
at currents greater than 20mA.
As shown in the Block Diagram, the Transmitter TX Input and
the Receiver RX Output of the Bus Transceiver Circuit inter-
face to the control logic. The TX input signal is wave shaped
for rise time, fall time and amplitude before it is converted
from voltage to current. The Wave Shaper with an external
programming resistor, R
S
controls the rise and fall time of
the BUS OUT output signal. The current source drive to the
Bus is voltage controlled by the Wave Shaped Voltage Refer-
ence to a maximum limit as specified for the J1850 Bus and
includes short-circuit current limiting.
The HIP7020 Receiver input, BUS IN is connected to the
J1850 Bus through an external resistor, R
F
and has a trip
point at one-half of the nominal Bus signal voltage which is
3.875V. The Receiver input is filtered to remove high fre-
quency Bus noise by the external resistor and an internal
capacitor. The Receiver Bus signal, after processing, is out-
put at the RX pin by the RX Buffer’s open collector driver.
The RX output is active low and requires an external pull-up
resistor returned to the control logic V
CC
supply. This pre-
vents power-up of the control logic by the transceiver if V
CC
supply voltage is removed.
The HIP7020 has a Loop-Back Enable Mode Switch to
return diagnostic information for the Bus Transceiver node.
For an active low or an open LB EN input, the Trans-
mit/Receive signals are internally “Looped-Back” to provide
a TX to RX return signal path independent of signals on the
Bus. A return path validation indicates proper action of the
Bus Transceiver apart from the J1850 Bus.
Pinout
HIP7020
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART
NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG. NO.
HIP7020AB
-40 to 125
8 Ld SOIC
M8.15
HIP7020AP
-40 to 125
8 Ld PDIP
E8.3
BATT
TX
R/F TIME
RX
1
2
3
4
8
7
6
5
GND
BUS OUT
LB EN
BUS IN
File Number
3642.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HIP7020AB | FPGA 2000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP7020AP | FPGA 2000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP7030A0 | J1850 8-Bit 68HC05 Microcontroller Emulator Version |
| HIP7030A0M | FPGA - 200000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP7030A2 | FPGA - 200000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HIP7020 DIE | 制造商:Harris Corporation 功能描述: |
| HIP7020AB | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 Bus Transceiver For Multiplex Wiring Systems |
| HIP7020AP | 制造商:Harris Corporation 功能描述: |
| HIP7030A0 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 8-Bit 68HC05 Microcontroller Emulator Version |
| HIP7030A0M | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 8-Bit 68HC05 Microcontroller Emulator Version |
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