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參數資料
| 型號： | HL14203 |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | Hyundai Electronics Industries System IC Division |
| 中文描述： | 現代電子工業系統集成電路部 |
| 文件頁數： | 14/26頁 |
| 文件大?。?/td> | 421K |
| 代理商： | HL14203 |
14
HL14203
P r e l i m i n a r y
Key input 1
3) In sleep mode
The pins KS1 to KS6 are set to high or low by the S0 and S1 bits in the
sleep mode control register.
If a key on one of the lines corresponding to a KS1 to KS6 pin which is set
high is pressed, the oscillator on the OSC pin is started and a key scan is
performed. Keys are scanned until all keys are released. Multiple key pre-
sses are recognized by determining whether multiple key data bits are set.
If a key is pressed for longer than 800T ( where T=1/fosc ) the HL14203
outputs a key data read request (a low level on SO) to the controller. The
controller acknowledges this request and reads the key data. However, if
CE is high during a serial data transfer, SO will be set high.
After the controller reads the key data, the key data read request is cleared
( SO is set high ) and the HL14203 performs another key scan. However
this does not clear sleep mode. Also note that SO, being an open-drain
output, requires a pull-up resistor ( between 1 and 10 K).
Sleep mode key scan example
Example : S0 = 0, S1 = 1 ( sleep with only KS6 high )
Key input 2
Key Scan
CE
SI
SO
800T
800T
800T
Write
address
Write
address
Read
address
Write
address
Read
address
Read
address
Key data read request
Key data read
Key data read
Key data read
Key data read request
Key data read request
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