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參數資料
| 型號： | HL15703 |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | RES,WIREWOUND,4OHMS,2.845KWV,5% TOL RoHS Compliant: No |
| 中文描述： | 現代電子工業系統集成電路部 |
| 文件頁數： | 19/26頁 |
| 文件大小： | 434K |
| 代理商： | HL15703 |
HL15703
P r e l i m i n a r y
19
11. Power Down Mode
Sleep mode is set up by setting S0 or S1 in the control data to 1. The segment
outputs will all go low and the common outputs will also go low, and the oscillator
on the OSC pin will stop ( it will be started by a key press). This reduces power
dissipation. This mode is cleared by sending control data with both S0 and S1 set
to 0. Note that the SEG1/P1 to SEG4/P4 outputs can be used as general purpose
output ports according to the state of the P0 and P1 control data bits, even in
sleep mode.
4) Output pin states during the reset period
SEG1/P1 to SEG4/P4 : Low *)
SEG5 to SEG55 : Low
COM1 to COM3 : Low
KS1/SEG56, KS2/SEG57 : Low *)
KS3 to KS5 : X
KS6 : High
SO : High
*) These output pins are forcibly set to the segment output function and held low.
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