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參數資料
| 型號： | HM624100HLJP-10 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 4M High Speed SRAM (1-Mword x 4-bit) |
| 中文描述： | 4分高速SRAM（1 - Mword × 4位） |
| 文件頁數： | 1/13頁 |
| 文件大小： | 74K |
| 代理商： | HM624100HLJP-10 |
HM624100H Series
4M High Speed SRAM (1-Mword
×
4-bit)
ADE-203-789D (Z)
Rev. 1.0
Sep. 15, 1998
Description
The HM624100H is a 4-Mbit high speed static RAM organized 1-Mword
×
4-bit. It has realized high speed
access time by employing CMOS process (4-transistor + 2-poly resistor memory cell) and high speed circuit
designing technology. It is most appropriate for the application which requires high speed and high density
memory, such as cache and buffer memory in system. The HM624100H is packaged in 400-mil 32-pin SOJ
for high density surface mounting.
Features
Single 5.0 V supply : 5.0 V
±
10 %
Access time 10/12/15 ns (max)
Completely static memory
No clock or timing strobe required
Equal access and cycle times
Directly TTL compatible
All inputs and outputs
Operating current : 200/180/160 mA (max)
TTL standby current : 70/60/50 mA (max)
CMOS standby ccurrent : 5 mA (max)
: 1.2 mA (max) (L-version)
Data retension current : 0.8 mA (max) (L-version)
Data retension voltage : 2.0 V (min) (L-version)
Center V
CC
and V
SS
type pinout
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PDF描述 |
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| HM624100HLJP-12 | 4M High Speed SRAM (1-Mword x 4-bit) |
| HM624100HLJP-15 | 4M High Speed SRAM (1-Mword x 4-bit) |
| HM624256A | 262144-word ×4-bit High Speed CMOS Static RAM(262144字 ×4位高速CMOS SRAM) |
| HM6264AFP-10 | Dual J-K Negative-Edge-Triggered Flip-Flops With Preset And Clear 16-CDIP -55 to 125 |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| HM624100HLJP-12 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4M High Speed SRAM (1-Mword x 4-bit) |
| HM624100HLJP-15 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4M High Speed SRAM (1-Mword x 4-bit) |
| HM624100JLP-30 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
| HM624100JLP-35 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
| HM624100JLP-45 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
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