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參數資料
| 型號： | HM62V8512B |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Quadruple Bus Buffer Gate With 3-State Outputs 14-SOIC -40 to 85 |
| 中文描述： | 四米的SRAM（512 - KWord的× 8位） |
| 文件頁數： | 1/17頁 |
| 文件大小： | 77K |
| 代理商： | HM62V8512B |
HM62V8512B Series
4 M SRAM (512-kword
×
8-bit)
ADE-203-905G (Z)
Rev. 6.0
Mar. 31, 2000
Description
The Hitachi HM62V8512B is a 4-Mbit static RAM organized 512-kword
×
8-bit. It realizes higher density,
higher performance and low power consumption by employing 0.35
μ
m Hi-CMOS process technology. The
device, packaged in a 525-mil SOP (foot print pitch width) or 400-mil TSOP TYPE II is available for high
density mounting. The HM62V8512B is suitable for battery backup system.
Features
Single 3.0 V supply: 2.7 V to 3.6 V
Access time: 70/85 ns (max)
Power dissipation
Active: 15 mW/MHz (typ)
Standby: 3
μ
W (typ)
Completely static memory. No clock or timing strobe required
Equal access and cycle times
Common data input and output: Three state output
Directly LV-TTL compatible: All inputs
Battery backup operation
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| HM62V8512BLRR-7SL | 4 M SRAM (512-kword x 8-bit) |
| HM62V8512BLRR-7UL | 4 M SRAM (512-kword x 8-bit) |
| HM62V8512BLRR-8 | 4 M SRAM (512-kword x 8-bit) |
| HM62V8512BLRR-8SL | 4 M SRAM (512-kword x 8-bit) |
| HM62V8512BLTT-7 | 4 M SRAM (512-kword x 8-bit) |
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