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參數(shù)資料
| 型號： | HM62V8512CLTT-7 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Octal Buffer/Driver With 3-State Outputs 20-PDIP -40 to 85 |
| 中文描述： | 四米的SRAM（512 - KWord的× 8位） |
| 文件頁數(shù)： | 1/16頁 |
| 文件大小： | 75K |
| 代理商： | HM62V8512CLTT-7 |
HM62V8512C Series
4 M SRAM (512-kword
×
8-bit)
ADE-203-1210A (Z)
Rev. 1.0
Jan. 31, 2001
Description
The Hitachi HM62V8512C is a 4-Mbit static RAM organized 512-kword
×
8-bit. It realizes higher density,
higher performance and low power consumption by employing CMOS process technology (6-transistor
memory cell). The device, packaged in a 525-mil SOP (foot print pitch width) or 400-mil TSOP TYPE II is
available for high density mounting. The HM62V8512C is suitable for battery backup system.
Features
Single 3.0 V supply: 2.7 V to 3.6 V
Access time: 55/70 ns (max)
Power dissipation
Active: 6.0 mW/MHz (typ)
Standby: 2.4 μW (typ)
Completely static memory. No clock or timing strobe required
Equal access and cycle times
Common data input and output: Three state output
Directly LV-TTL compatible: All inputs
Battery backup operation
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| HM62V8512CLTT-7SL | 4 M SRAM (512-kword x 8-bit) |
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| HM62V8512CLFP-7 | 4 M SRAM (512-kword x 8-bit) |
| HM62V8512CLFP-7SL | 4 M SRAM (512-kword x 8-bit) |
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