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參數(shù)資料
| 型號(hào)： | HMC624LP4E |
| 廠商： | Hittite Microwave Corporation |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大小： | 863K |
| 描述： | ATTENUATOR DGTL 6BIT 24QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 衰減值： | 0.5dB ~ 31.5dB |
| 頻率范圍： | 0 ~ 6GHz |
| 阻抗： | 50 歐姆 |
| 封裝/外殼： | 24-VQFN 裸露焊盤(pán) |
| 其它名稱： | 1127-1061-6 |
5
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
HMC624LP4 / 624LP4E
v12.0812
0.5 dB LSB GaAs MMIC 6-BIT
DIGITAL ATTENUATOR, DC - 6 GHz
Bias Voltage
Vdd (V)
Idd (Typ.) (mA)
3
1.8
5
2.0
PUP Truth Table
Power-Up States
Control Voltage Input
Reference
Insertion
Loss
D5
D4
D3
D2
D1
D0
High
High
High
High High
High
0 dB
High
High
High
High High
Low
-0.5 dB
High
High
High
High
Low
High
-1 dB
High
High
High
Low
High
High
-2 dB
High
High
Low
High High
High
-4 dB
High
Low
High
High High
High
-8 dB
Low
High
High
High High
High
-16 dB
Low
Low
Low
Low
Low
Low
-31.5 dB
Any combination of the above states will provide an attenuation
equal to the sum of the bits selected.
Truth Table
Timing Diagram (Latched Parallel Mode)
Parallel Mode
(Direct Parallel Mode & Latched Parallel Mode)
Note: The parallel mode is enabled when P/S is set to low.
Direct Parallel Mode - The attenuation state is changed by the control voltage inputs D0-D5 directly. The LE (Latch
Enable) must be at a logic high at all times to control the attenuator in this manner.
Latched Parallel Mode - The attenuation state is selected using the control voltage inputs D0-D5 and set while the
LE is in the Low state. The attenuator will not change state while LE is Low. Once all Control Voltage Inputs are at the
desired states the LE is pulsed. See timing diagram above for reference.
LE
PUP1
PUP2
Relative Attenuation
0
0
0
-31.5
0
1
0
-24
0
0
1
-16
0
1
1
Insertion Loss
1
X
X
0 to -31.5 dB
Note: The logic state of D0 - D5 determines the power-
up state per truth table shown below when LE is high
at power-up.
If LE is set to logic LOW at power-up, the logic state of
PUP1 and PUP2 determines the power-up state of the
part per PUP truth table. If the LE is set to logic HIGH
at power-up, the logic state of D0-D5 determines the
power-up state of the part per truth table. The attenu-
ator latches in the desired power-up state approxi-
mately 200 ms after power-up.
Power-On Sequence
The ideal power-up sequence is: GND, Vdd, digital
inputs, RF inputs. The relative order of the digital
inputs are not important as long as they are powered
after Vdd / GND
Parameter
Min.
[1]
Typ.
[1]
Min. serial period, t
SCK
70 ns
Control set-up time, t
CS
15 ns
Control hold-time, t
CH
20 ns
LE setup-time, t
LN
15 ns
Min. LE pulse width, t
LEW
10 ns
Min LE pulse spacing, t
LES
630 ns
Serial clock hold-time from LE, t
CKN
10 ns
Hold Time, t
PH.
0 ns
Latch Enable Minimum Width, t
LEN
10 ns
Setup Time, t
PS
2 ns
Control Voltage Table
State
Vdd = +3V
Vdd = +5V
Low
0 to 0.5V @ <1 礎(chǔ)
0 to 0.8V @ <1 礎(chǔ)
High
2 to 3V @ <1 礎(chǔ)
2 to 5V @ <1 礎(chǔ)
[1] Vdd = 5V
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