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參數資料
| 型號： | HMS81024E |
| 廠商： | Hynix Semiconductor Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | HYNIX SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | Hynix半導體公司的8位單芯片微控制器 |
| 文件頁數： | 50/77頁 |
| 文件大小： | 1112K |
| 代理商： | HMS81024E |
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HMS81004E/08E/16E/24E/32E
JUNE 2001 Ver 1.00
47
14. INTERRUPTS
The HMS81004E/08E/16E/24E/32E interrupt circuits
consist of Interrupt Mode Register (MOD), Interrupt en-
able register (IENH, IENL), Interrupt request flags of
IRQH, IRQL, Priority circuit and Master enable flag ("I"
flag of PSW). 8 interrupt sources are provided. The config-
uration of interrupt circuit is shown in Figure 14-1 .
The HMS81004E/08E/16E/24E/32E contains 8 interrupt
sources; 3 externals and 5 internals. Nested interrupt ser-
vices with priority control is also possible. Software inter-
rupt is non-maskable interrupt, the others are all maskable
interrupts.
- 8 interrupt source (2Ext, 3Timer, BIT, WDT and
Key Scan)
- 8 interrupt vector
- Nested interrupt control is possible
- Programmable interrupt mode
(Hardware and software interrupt accept mode)
- Read and write of interrupt request flag are possible.
- In interrupt accept, request flag is automatically cleared.
Figure 14-1 Block Diagram of Interrupt
INT1
INT2
Watch Dog Timer
WDTR
IENL
Interrupt Enable
Register (Lower byte)
Interrupt Enable
Register (Higher byte)
IRQL
IRQH
Interrupt
Vector
Address
Generator
Internal bus line
Internal bus line
Release STOP
To CPU
Interrupt Master
Enable Flag
I-flag
IENH
P
I-flag is in PSW, it is cleared by “DI”, set by
“EI” instruction. When it goes interrupt service,
I-flag is cleared by hardware, thus any other
interrupt are inhibited. When interrupt service is
completed by “RETI” instruction, I-flag is set to
“1” by hardware.
INT2R
T0R
BITR
KSCNR
Key Scan
Basic Interval Timer
INT1R
T2R
T1R
Timer 2
Timer 1
Timer 0
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