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參數(shù)資料
型號(hào)： HMS87C1304AD
廠商： HYNIX SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
中文描述： 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PDSO24
封裝： SOP-24
文件頁(yè)數(shù)： 49/70頁(yè)
文件大小： 977K
代理商： HMS87C1304AD
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
Jan. 2001
Preliminary
49
15. INTERRUPTS
The HMS87C1304A and HMS87C1302A interrupt cir-
cuits consist of Interrupt enable register (IENH, IENL), In-
terrupt request flags of IRQH, IRQL, Interrupt Edge
Selection Register (IEDS), priority circuit and Master en-
able flag(“I” flag of PSW). The configuration of interrupt
circuit is shown in Figure 15-1 and Interrupt priority is
shown in Table 15-1 .
The External Interrupts INT0 and INT1 can each be transi-
tion-activated (1-to-0, 0-to-1 and both transition).
The flags that actually generate these interrupts are bit
INT0IF and INT1IF in Register IRQH. When an external
interrupt is generated, the flag that generated it is cleared
by the hardware when the service routine is vectored to
only if the interrupt was transition-activated.
The Timer 0 and Timer 1 Interrupts are generated by T0IF
and T1IF, which are set by a match in their respective tim-
er/counter register. The AD converter Interrupt is generat-
ed by ADIF which is set by finishing the analog to digital
conversion. The Watch dog timer Interrupt is generated by
WDTIF which set by a match in Watch dog timer register
(when the bit WDTON is set to “0”). The Basic Interval
Timer Interrupt is generated by BITIF which is set by a
overflowing of the Basic Interval Timer Register(BITR).
Figure 15-1 Block Diagram of Interrupt Function
The interrupts are controlled by the interrupt master enable
flag I-flag (bit 2 of PSW), the interrupt enable register
(IENH, IENL) and the interrupt request flags (in IRQH,
IRQL) except Power-on reset and software BRK interrupt.
Interrupt enable registers are shown in Figure 15-2 . These
registers are composed of interrupt enable flags of each in-
terrupt source, these flags determines whether an interrupt
will be accepted or not. When enable flag is “0”, a corre-
BIT
BITIF
WDTIF
WDT
A/D Converter
Timer 1
Timer 0
External Int. 1
External Int. 0
IENH
Interrupt Enable
Register (Higher byte)
Interrupt Enable
Register (Lower byte)
IRQH
IRQL
Interrupt
Vector
Address
Generator
Internal bus line
Internal bus line
Release STOP
To CPU
Interrupt Master
Enable Flag
I Flag
IENL
P
I-flag is in PSW, it is cleared by “DI”, set by
“EI” instruction.When it goes interrupt service,
I-flag is cleared by hardware, thus any other
interrupt are inhibited. When interrupt service is
completed by “RETI” instruction, I-flag is set to
“1” by hardware.
INT0IF
INT1IF
T0IF
T1IF
ADIF
7
6
5
4
7
6
5
IEDS
Preimnary
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