
HMS91C7134
November.2001 ver1.0
1
HMS91C7134
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
FOR MONITOR
1. OVERVIEW
1.1 Description
The HMS9xC7134 is a single-chip microcontroller of the 80C51 family, which is dedicated for monitor application. It is particularly suit-
able for multi-sync computer monitor controller. This contains DDC interfaces to the PC host, sync-detector and sync-processor for auto-
sync application, ADC, static PWM, dynamic PWM and I
2
C bus interface for control of the video and deflection functions of the monitor.
1.2 Features
80C51 core
32K bytes of ROM for HMS91C7134
(32K bytes of EPROM for HMS97C7134)
256 bytes of RAM and 256 bytes of XRAM for
DDC operation
Uses an external crystal of 12.0 MHz
One DDC compliant interface :
-
Fully supports DDC1 with dedicated hardware
- DDC2B, DDC2AB and DDC2B+ compliant dedi-
cated hardware based on an I
2
C bus interface
- RAM buffer with programmable size, 128 bytes
or 256 bytes, which can be used for DDC opera-
tion or shared as system RAM
On-chip sync processor
-
HSYNC frequency with 12-bit resolution
- VSYNC frequency with 12-bit resolution
- HSYNC and VSYNC polarity
- HSYNC and VSYNC presence detection
- Composite sync separation
- Free running sync. generation
- Clamping pulse output
- Pattern generation
- Separate input for a SOG signal
- Missing pulse insertion option
- HSYNC/ VSYNC change interrupt
One multi-master/slave I2C interface (up to
400K bit/s) for control of other system IC’s
Eight 8-bit Static PWM outputs for digital con-
trol applications
Two 8-bit Dynamic PWM outputs for various
waveform generation
One 8-bit ADC with 4 input channels
LED driver port ; two port lines with
15 mA drive capability
One 8-bit port only for I/O function
24 derivative I/O ports configurable for alterna-
tive functions
Watchdog timer (524ms max.)
On-chip low VDD voltage detect and reset
(reset period: 524ms)
Operating temperature : 0
to 70
Special idle and power-down modes with low
power consumption
Single power supply : 4.5V to 5.5V
Device name
ROM Size
RAM
Size
I/O
OTP
Package
HMS91C7134
32K bytes
Mask ROM
512 bytes
30(42DIP)
32(42SDIP)
HMS97C7134
40DIP(HMS91C7134),
42SDIP(HMS91C7134K)