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參數資料
| 型號： | HPA00021DGGR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 14-BIT REGISTERED BUFFER WITH SSTL 2 INPUTS AND OUTPUTS |
| 中文描述： | 14位注冊緩沖區薩里衛星技術有限公司2輸入和輸出 |
| 文件頁數： | 1/9頁 |
| 文件大小： | 156K |
| 代理商： | HPA00021DGGR |
SCES344E – DECEMBER 2000 – REVISED NOVEMBER 2002
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Member of the Texas Instruments
Widebus
Family
Supports SSTL_2 Data Inputs
Outputs Meet SSTL_2 Class II
Specifications
Differential Clock (CLK and CLK) Inputs
Supports LVCMOS Switching Levels on the
RESET Input
RESET Input Disables Differential Input
Receivers, Resets All Registers, and
Forces All Outputs Low
Flow-Through Architecture Optimizes PCB
Layout
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description
This 14-bit registered buffer is designed for 2.3-V
to 2.7-V V
CC
operation.
All inputs are SSTL_2, except the LVCMOS reset
(RESET) input. All outputs are SSTL_2, Class II
compatible.
The SN74SSTV16857 operates from a differential clock (CLK and CLK). Data are registered at the crossing
of CLK going high and CLK going low.
The device supports low-power standby operation. When RESET is low, the differential input receivers are
disabled and undriven (floating) data, clock, and reference voltage (V
REF
) inputs are allowed. In addition, when
RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must
be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in
the low state during power up.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
0
°
C to 70
°
C
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
TSSOP – DGG
Tape and reel
SN74SSTV16857DGGR
SSTV16857
Copyright
2002, Texas Instruments Incorporated
Widebus is a trademark of Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DGG PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Q1
Q2
GND
V
DDQ
Q3
Q4
Q5
GND
V
DDQ
Q6
Q7
V
DDQ
GND
Q8
Q9
V
DDQ
GND
Q10
Q11
Q12
V
DDQ
GND
Q13
Q14
D1
D2
GND
V
CC
D3
D4
D5
D6
D7
CLK
CLK
V
CC
GND
V
REF
RESET
D8
D9
D10
D11
D12
V
CC
GND
D13
D14
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