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參數(shù)資料
型號(hào): HPC36400E
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 微控制器/微處理器
英文描述: IND,Non-Specified,4.7uH,20+% Tol,20-% Tol,2725-Case RoHS Compliant: Yes
中文描述: 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PQCC68
封裝: PLASTIC, LCC-68
文件頁(yè)數(shù): 1/30頁(yè)
文件大小: 362K
代理商: HPC36400E
TLDD10422
HPC36400EHPC46400E
High-Performance
Communications
MicroController
PRELIMINARY
November 1992
HPC36400EHPC46400E
High-Performance Communications MicroController
General Description
The HPC46400E is an upgraded HPC16400 Features have
been added to support V120 the 8-bit mode has been en-
hanced to support all instructions and the UART has been
changed to provide more flexibility and power
The
HPC46400E is fully upward compatible with the HPC16400
The HPC46400E has 4 functional blocks to support a wide
range of communication application-2 HDLC channels 4
channel DMA controller to facilitate data flow for the HDLC
channels programmable serial interface and UART
The serial interface decoder allows the 2 HDLC channels to
be used with devices using interchip serial link for point-to-
point and multipoint data exchanges The decoder gener-
ates enable signals for the HDLC channels allowing multi-
plexed D and B channel data to be accessed
The HDLC channels manage the link by providing sequenc-
ing using the HDLC framing along with error control based
upon a cyclic redundancy check (CRC) Multiple address
recognition modes and both bit and byte modes of opera-
tion are supported
The HPC36400E and HPC46400E are available in 68-pin
PLCC and 80-pin PQFP packages
Features
Y
HPCTM familycore features
16-bit data bus ALU and registers
64 kbytes of external memory addressing
FAST200 MHz system clock
Four 16-bit timercounters with WATCHDOGTM logic
MICROWIREPLUSTM serial IO interface
CMOSlow power with two power save modes
Y
Two full duplex HDLC channels
Optimized for ISDN X25 V120 and LAPD
applications
Programmable frame address recognition
Up to 465 Mbps serial data rate
Built in diagnostics
Synchronous bypass mode
Optional CRC generation
Received CRC bytes can be read by the CPU
Y
Four channel DMA controller
Y
8- or 16-bit external data bus
Y
UART
Full duplex
7 8 or 9 data bits
Even odd mark space or no parity
78 1 or 2 stop bit generation
Accurate internal baud rate generation up to 625k
baud without penalty of using expensive crystal
Synchronous and asynchronous modes of operation
Y
Serial Decoder
Supports 6 popular time division multiplexing proto-
cols for inter-chip communications
Optional rate adaptation of 64 kbits data rate to
56 kbits
Y
Over
Mbyte of extended addressing
Y
Easy interface to National’s DASL ‘U’ and ‘S’ trans-
ceiversTP3400 TP3410 and TP3420
Y
Commercial (0 Cto a70 C) and industrial (b40 Cto
a
85 C)
Block Diagram
TLDD10422 – 1
TapePak
and TRI-STATE
are registered trademarks of National Semiconductor Corporation
HPCTM MICROWIREPLUSTM and WATCHDOGTM are trademarks of National Semiconductor Corporation
IBM
PC-AT
are registered trademarks of International Business Machines Corporation
Sun
is a registered trademark of Sun Microsystems
SunOSTM is a trademark of Sun Microsystems
UNIX
is a registered trademark of ATT Bell Laboratories
C1995 National Semiconductor Corporation
RRD-B30M115Printed in U S A
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