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參數資料
| 型號： | HPFC-5166A |
| 英文描述： | 66 MHz PCI to Fibre Channel Controller(66 MHz PCI到光纖通道控制器) |
| 中文描述： | 66 MHz的PCI控制器，以光纖通道（66 MHz的PCI到光纖通道控制器） |
| 文件頁數： | 1/4頁 |
| 文件大?。?/td> | 168K |
| 代理商： | HPFC-5166A |
Features
Supports All Fibre Channel
Topologies; Arbitrated Loop
(FC-AL) and N_Port Fabric
Attachment
Supports Class 3 and Class 2
(via Software)
66 MHz, 32/64-Bit PCI
Interface
1 Gigabit/Second Fibre
Channel Rate
Full Duplex Support with
Parallel Inbound and
Outbound Processing
Complete Hardware Handling
of Entire SCSI I/O via FCP
On-Chip Assists
Full Initiator and Target
Mode Functionality
Applications
Motherboard Integration
Host-Based Adapters
Storage Subsystems
I
2
O Designs
Description
The HPFC-5166A, Tachyon TS, is
a second-generation controller that
leverages extensive experience in
Fibre Channel, established with
the original TACHYON controller.
Tachyon TS carries forward the
assurance of interoperability and
true Fibre Channel performance.
HPFC-5166A
Tachyon TS
66 MHz PCI to Fibre Channel
Controller
Technical Data
Tachyon TS focuses on mass
storage applications for any
topology that require Class 3 and
Class 2 (via software), and SCSI
upper layer protocol handling.
Coupled with a high performance
66 MHz, 32/64-bit PCI bus inter-
face, Tachyon TS provides a cost-
effective, high-performance mass
storage solution.
TACHYON Architecture
Tachyon TS continues with the
TACHYON architecture, a
complete hardware-based state
machine design. This architecture
does not require an additional on-
board microprocessor and there-
fore avoids reduced performance
issues relating to processor cycles
per second and access time to
firmware. Rather, the TACHYON
architecture is designed to be a
single chip Fibre Channel solution.
Tachyon TS provides the highest
levels of concurrency via
numerous independent functional
blocks providing parallel
processing of data, control, and
commands. In addition, these
blocks process at hardware speeds
versus firmware speeds, and
automate the entire SCSI I/O in
hardware. The result is minimized
latency and I/O overhead, coupled
with the highest levels of parallel-
ism to provide maximum I/O rates
and bandwidth.
FC-AL Features
In addition to the high-perfor-
mance architecture, Tachyon TS
builds on the Tachyon TL with
Public Loop, multiple I/Os in the
same loop arbitration cycle, Loop
Map, Loop Broadcast, and Loop
Directed Reset while offering 66
MHz PCI connectivity. These
features allow the designer to
achieve higher performance in an
arbitrated loop topology.
Physical Layer
The physical layer interface is the
popular 10-bit wide specification
that allows interfacing to a low-
cost serializer/deserializer
(SerDes) IC. The stable, demon-
strated performance of the
SerDes with BER>10
-14
avoids
the random occurrences and
configuration dependent limita-
tions introduced by current
integrated implementations that
exhibit degraded signal integrity
and jitter tolerance.
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| HPH-2540-80P-1 | HIGH PROFILE PIN HEADER |
| HPH-2540-80P-2 | HIGH PROFILE PIN HEADER |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| HPFC-5166B | 制造商:Rochester Electronics LLC 功能描述: 制造商:Agilent Technologies 功能描述:Manufacturer Supplied Status Information 制造商:PMC-Sierra 功能描述: |
| HPFC-5200C | 制造商:Agilent Technologies 功能描述:Manufacturer Supplied Status Information |
| HPFC-5200D/2.3 | 制造商:Agilent Technologies 功能描述:Telecomm/Datacomm, Other |
| HPFC-5400 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Tachyon DX2 Dual Channel Fibre Channel IC |
| HPFC-5400D | 制造商:Agilent Technologies 功能描述:IC,CONTROLLER,2GB/S DUAL CHANNEL FIBRE CHANNEL,TACHYON DX2 |
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