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參數資料
| 型號： | HPLL-8001 |
| 英文描述： | PLL Frequency Synthesizer(鎖相環頻率合成器) |
| 中文描述： | 鎖相環頻率合成器（鎖相環頻率合成器） |
| 文件頁數： | 1/12頁 |
| 文件大小： | 77K |
| 代理商： | HPLL-8001 |
PLL Frequency Synthesizer
Technical Data
Features
Low Operating Current
Consumption ( 4 mA, typ.)
High Input Sensitivity, High
Input Frequencies ( 50 MHz)
Synchronous Programming of
the Counters ( n-, n/a-,
r-counters)
Switchable Modulus Trigger
E dge
Large Dividing Ratios for
Small Channel Spacing,
A counter 0 to 127, N counter
3 to 16,380, R counter 3 to
65,535
Serial Control 3-wire Bus:
Data, Clock ( <10 MHz) , Enable
Switchable Polarity and
Programmable Phase Detector
Current
2 Programmable Outputs
Digital Phase Detector
Output Signals ( e.g. for
E xternal Charge Pump)
DRFI, DVFI Outputs ( e.g. for
Prescaler Standby)
Lock Detect Output with
Gated Anti-backlash Pulse
( quasi digital lock detect)
Applications
GSM Handsets and Base
Stations
PCS/PCN
DE CT
Wireless LAN
HPLL-8001
Description
The HPLL-8001 is a phase-locked
loop (PLL) frequency synthesizer
intended for use in a frequency
generation loop with an external
dual modulus prescaler and VCO.
The VCO frequency is divided by
the dual modulus prescaler, which
is then fed to the internal A and N
counters. The reference frequency
is fed to an internal R counter to
define the channel spacing. Both
frequencies are compared in the
phase detector which drives the
charge pump. A lock detect is
provided to monitor the lock state
of the loop. All blocks are
programmed by a serial 3-wire
bus interface.
Plastic SOP-14
Pin Configuration
Functional Block Diagram
HPLL
8001
YYWW
VCOI
MOD
PO1
PO2
H
8
Y
EN
VSS
REFI
LD
AVSS
PD
VDD
CLK
DATA
AVDD
1
7
14
8
DATA
CLOCK
ENABLE
REFI
VCOI
VDD
VSS AVDD AVSS
MOD
DVFI
DRFI
PO2
LD
PO1
PD
c7 bit A
Serial
Control Logic
14 bit N
counter
Analog
Control
Logic
16 bit R
Modulus
Control
Phase
Detector
Charge
Pump
Lock
Detect
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