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參數(shù)資料
| 型號： | HS-1135RH |
| 廠商： | Intersil Corporation |
| 英文描述： | Radiation Hardened, High Speed, Low Power Current Feedback Amplifier with Programmable Output Limiting |
| 中文描述： | 輻射加固，高速，低功耗電流反饋放大器，具有可編程輸出限制 |
| 文件頁數(shù)： | 2/5頁 |
| 文件大小： | 63K |
| 代理商： | HS-1135RH |
2
Clamp Operation
General
The HS-1135RH features user programmable output clamps
to limit output voltage excursions. Clamping action is obtained
by applying voltages to the V
H
and V
L
terminals (pins 8 and 5)
of the amplifier. V
H
sets the upper output limit, while V
L
sets
the lower clamp level. If the amplifier tries to drive the output
above V
H
, or below V
L
, the clamp circuitry limits the output
voltage at V
H
or V
L
( the clamp accuracy), respectively. The
low input bias currents of the clamp pins allow them to be
driven by simple resistive divider circuits, or active elements
such as amplifiers or DACs.
Clamp Circuitry
Figure 1 shows a simplified schematic of the HS-1135RH
input stage, and the high clamp (V
H
) circuitry. As with all
current feedback amplifiers, there is a unity gain buffer (Q
X1
- Q
X2
) between the positive and negative inputs. This buffer
forces -IN to track +IN, and sets up a slewing current of (V
-
IN
- V
OUT
)/R
F
. This current is mirrored onto the high
impedance node (Z) by Q
X3
-Q
X4
, where it is converted to a
voltage and fed to the output via another unity gain buffer. If
no clamping is utilized, the high impedance node may swing
within the limits defined by Q
P4
and Q
N4
. Note that when the
output reaches it’s quiescent value, the current flowing
through -IN is reduced to only that small current (-I
BIAS
)
required to keep the output at the final voltage.
Tracing the path from V
H
to Z illustrates the effect of the
clamp voltage on the high impedance node. V
H
decreases
by 2V
BE
(QN6 and QP6) to set up the base voltage on QP5.
QP5 begins to conduct whenever the high impedance node
reaches a voltage equal to QP5’s base + 2V
BE
(QP5 and
QN5). Thus, QP5 clamps node Z whenever Z reaches V
H
.
R1 provides a pull-up network to ensure functionality with
the clamp inputs floating. A similar description applies to the
symmetrical low clamp circuitry controlled by V
L
.
When the output is clamped, the negative input continues to
source a slewing current (I
CLAMP
) in an attempt to force the
output to the quiescent voltage defined by the input. Q
P5
must
sink this current while clamping, because the -IN current is
always mirrored onto the high impedance node. The clamping
current is calculated as (V
-IN
- V
OUT
)/R
F
. As an example, a
unity gain circuit with V
IN
= 2V, V
H
= 1V, and R
F
= 510
would
have I
CLAMP
= (2-1)/510
= 1.96mA. Note that I
CC
will
increase by I
CLAMP
when the output is clamp limited.
Clamp Accuracy
The clamped output voltage will not be exactly equal to the
voltage applied to V
H
or V
L
. Offset errors, mostly due to V
BE
mismatches, necessitate a clamp accuracy parameter which is
found in the device specifications. Clamp accuracy is a function
of the clamping conditions. Referring again to Figure 1, it can
be seen that one component of clamp accuracy is the V
BE
mismatchbetweentheQ
X6
transistors,andtheQ
X5
transistors.
If the transistors always ran at the same current level there
would be no V
BE
mismatch, and no contribution to the
inaccuracy. The Q
X6
transistors are biased at a constant
current, but as described earlier, the current through Q
X5
is
equivalent to I
CLAMP
. V
BE
increases as I
CLAMP
increases,
causingtheclampedoutputvoltagetoincreaseaswell.I
CLAMP
is a function of the overdrive level (V
-IN
-V
OUTCLAMPED
) and
R
F
,so clamp accuracy degrades as the overdrive increases, or
as R
F
decreases. As an example, the specified accuracy of
±
60mVfora2XoverdrivewithR
F
= 510
degradesto
±
220mV
for R
F
= 240
at the same overdrive, or to
±
250mV for a 3X
overdrive with R
F
= 510
.
Consideration must also be given to the fact that the clamp
voltages have an effect on amplifier linearity. The
“Nonlinearity Near Clamp Voltage” curve in the data sheet
illustrates the impact of several clamp levels on linearity.
Clamp Range
Unlike some competitor devices, both V
H
and V
L
have usable
ranges that cross 0V. While V
H
must be more positive than V
L
,
both may be positive or negative, within the range restrictions
indicated in the specifications. For example, the HS-1135RH
could be limited to ECL output levels by setting V
H
= -0.8V and
V
L
= -1.8V. V
H
and V
L
may be connected to the same voltage
(GND for instance) but the result won’t be in a DC output
voltage from an AC input signal. A 150 - 200mV AC signal will
still be present at the output.
Recovery from Overdrive
The output voltage remains at the clamp level as long as the
overdrive condition remains. When the input voltage drops
below the overdrive level (V
CLAMP
/A
VCL
) the amplifier will
return to linear operation. A time delay, known as the
Overdrive Recovery Time, is required for this resumption of
linear operation. The plots of “Unclamped Performance” and
“Clamped Performance” highlight the HS-1135RH’s
+1
+IN
V-
V+
Q
P1
Q
N1
V-
Q
N3
Q
P3
Q
P4
Q
N2
Q
P2
Q
N4
Q
P5
Q
N5
Z
V+
-IN
V
OUT
I
CLAMP
R
F
(EXTERNAL)
Q
P6
Q
N6
V
H
R
1
50K
(30K
FOR V
L
)
200
FIGURE 1. HS-1135RH SIMPLIFIED V
H
CLAMP CIRCUITRY
HS-1135RH
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