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參數資料
| 型號： | HS1-80C85RH-Q |
| 廠商： | INTERSIL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Radiation Hardened 8-Bit CMOS Microprocessor |
| 中文描述： | 8-BIT, 2 MHz, MICROPROCESSOR, CDIP40 |
| 封裝： | SIDE BRAZED, METAL SEALED, CERAMIC, DIP-40 |
| 文件頁數： | 7/16頁 |
| 文件大小： | 758K |
| 代理商： | HS1-80C85RH-Q |
7
TABLE 1. ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
(NOTE 1)
CONDITIONS
TEMPERATURE (
o
C)
MIN
MAX
UNITS
Input Capacitance
CIN
VDD = Open, f = 1MHz
T
A
= 25
-
12
pF
I/O Capacitance
CI/O
VDD = Open, f = 1MHz
T
A
= 25
-
13
pF
Output Capacitance
COUT
VDD = Open, f = 1MHz
T
A
= 25
-
12
pF
NOTE:
1. All measurements referenced to device ground.
TABLE 2. INTERRUPT PRIORITY, RESTART ADDRESS, AND SENSITIVITY
NAME
PRIORITY
ADDRESS BRANCHED TO (1) WHEN
INTERRUPT OCCURS
TYPE TRIGGER
TRAP
1
24H
Rising edge and high level until sampled.
RST 7.5
2
3CH
Rising edge (latched).
RST 6.5
3
34CH
High level until sampled.
RST 5.5
4
2CH
High level until sampled.
INTR
5
See Note 2
High level until sampled.
NOTES:
2. The processor pushes the PC on the stack before branching to the indicated address.
3. The address branched to depends on the instruction provided to the CPU when the interrupt is acknowledged.
TABLE 3. BUS TIMING SPECIFICATION AS A t
CYC
DEPENDENT
SYMBOL
HS-8OC85RH
SYMBOL
HS-8OC85RH
tAL
(1/2)T- 175
Minimum
tCC
(3/2 + N)T - 175
Minimum
tLA
(1/2)T- 175
Minimum
tCL
(1/2)T - 190
Minimum
tLL
(1/2)T-50
Minimum
tARY
(3/2)T - 500
Maximum
tLCK
(1/2)T- 125
Minimum
tHACK
(1/2)T - 160
Minimum
tLC
(1/2)T- 100
Minimum
tHABF
(1/2)T +125
Maximum
tAD
(5/2 + N)T - 375
Maximum
tHABE
(1/2)T +125
Maximum
tRD
(3/2 + N)T - 375
Maximum
tAC
(2/2)T - 200
Minimum
tRAE
(1/2)T- 130
Minimum
t1
(1/2)T-210
Minimum
tCA
(1/2)T - 100
Minimum
t2
(1/2)T- 150
Minimum
tDW
(3/2 + N)T - 175
Minimum
tRV
(3/2)T - 200
Minimum
tWD
(1/2)T-100
Minimum
tLDR
(4/2)T - 325
Maximum
NOTE: N is equal to the total WAIT states T = tCYC.
HS-80C85RH
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