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參數資料
| 型號： | HS9-26CLV31RH-Q |
| 廠商： | INTERSIL CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | PANEL |
| 中文描述： | QUAD LINE DRIVER, CDFP16 |
| 封裝： | CERAMIC, DFP-16 |
| 文件頁數： | 2/2頁 |
| 文件大?。?/td> | 35K |
| 代理商： | HS9-26CLV31RH-Q |
2
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
www.intersil.com
Die Characteristics
DIE DIMENSIONS:
96.5 mils x 195 mils x 21 mils
(2450 x 4950)
INTERFACE MATERIALS:
Glassivation:
Type: PSG (Phosphorus Silicon Glass)
Thickness: 8k
±
1k
Metallization:
Bottom: Mo/TiW
Thickness: 5800
±
1k
Top: AlSiCu (Top)
Thickness: 10k
±
1k
Substrate:
AVLSI1RA
Backside Finish:
Silicon
ASSEMBLY RELATED INFORMATION:
Substrate Potential (Powered Up):
V
DD
ADDITIONAL INFORMATION:
Worst Case Current Density:
<2.0 x 10
5
A/cm
2
Bond Pad Size:
110
μ
m x 100
μ
m
Metallization Mask Layout
HS-26CLV31RH
(14) DO
(13) DO
(12) ENABLE
(11) CO
(10) CO
AO (2)
AO (3)
ENABLE (4)
BO (5)
BO (6)
B
N
C
N
(
(
D
(
(
D
HS-26CLV31RH
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