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參數資料
| 型號： | HSC-INTERFACEBOARD |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 1.75 MSPS, 4 mW 10-Bit/12-Bit Parallel ADCs |
| 中文描述： | 1.75 MSPS的，4 10-Bit/12-Bit并行模數轉換器毫瓦 |
| 文件頁數： | 1/16頁 |
| 文件大小： | 197K |
| 代理商： | HSC-INTERFACEBOARD |
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD7470/AD7472
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2000
1.75 MSPS, 4 mW
10-Bit/12-Bit Parallel ADCs
FUNCTIONAL BLOCK DIAGRAM
T/H
10-/12-BIT
SUCCESSIVE
APPROXIMATION
ADC
OUTPUT
DRIVERS
AD7470/AD7472
V
IN
CONVST
AGND
DGND
AV
DD
DV
DD
REF IN
V
DRIVE
DB9 (DB11)
DB0
CLK IN
CS
RD
BUSY
CONTROL
LOGIC
AD7470 IS A 10-BIT PART WITH DB0 TO DB9 AS OUTPUTS.
AD7472 IS A 12-BIT PART WITH DB0 TO DB11 AS OUTPUTS.
FEATURES
Specified for V
DD
of 2.7 V to 5.25 V
1.75 MSPS for AD7470 (10-Bit)
1.5 MSPS for AD7472 (12-Bit)
Low Power
AD7470: 3.34 mW Typ at 1.5 MSPS with 3 V Supplies
7.97 mW Typ at 1.75 MSPS with 5 V Supplies
AD7472: 3.54 mW Typ at 1.2 MSPS with 3 V Supplies
8.7 mW Typ at 1.5 MSPS with 5 V Supplies
Wide Input Bandwidth
70 dB Typ SNR at 500 kHz Input Frequency
Flexible Power/Throughput Rate Management
No Pipeline Delays
High Speed Parallel Interface
Sleep Mode: 50 nA Typ
24-Lead SOIC and TSSOP Packages
GENERAL DESCRIPTION
The AD7470/AD7472 are 10-bit/12-bit high speed, low power,
successive-approximation ADCs. The parts operate from a
single 2.7 V to 5.25 V power supply and feature throughput rates
up to 1.5 MSPS for the 12-bit AD7472 and up to 1.75 MSPS for
the 10-bit AD7470. The parts contain a low noise, wide band-
width track/hold amplifier that can handle input frequencies in
excess of 1 MHz.
The conversion process and data acquisition are controlled
using standard control inputs allowing easy interfacing to
microprocessors or DSPs. The input signal is sampled on the
falling edge of
CONVST
and conversion is also initiated at
this point. The BUSY goes high at the start of conversion and
goes low 531.66 ns after falling edge of
CONVST
(AD7472 with
a clock frequency of 26 MHz) to indicate that the conversion is
complete. There are no pipelined delays associated with the part.
The conversion result is accessed via standard
CS
and
RD
sig-
nals over a high speed parallel interface.
The AD7470/AD7472 uses advanced design techniques to
achieve very low power dissipation at high throughput rates. With
3 V supplies and 1.5 MSPS throughput rate, the AD7470 typi-
cally consumes, on average, just 1.1 mA. With 5 V supplies and
1.75 MSPS, the average current consumption is typically
1.6 mA. The part also offers flexible power/throughput rate
management. Operating the AD7470 with 3 V supplies and
500 kSPS throughput reduces the current consumption to 713
μ
A.
At 5 V supplies and 500 kSPS, the part consumes 944
μ
A.
It is also possible to operate the parts in an auto sleep mode,
where the part wakes up to do a conversion and automatically
enters sleep mode at the end of conversion. Using this method
allows very low power dissipation numbers at lower throughput
rates. In this mode, the AD7472 can be operated with 3 V sup-
plies at 100 kSPS, and consume an average current of just 124
μ
A.
At 5 V supplies and 100 kSPS, the average current consumption
is 171
μ
A.
The analog input range for the part is 0 to REF IN. The +2.5 V
reference is applied externally to the REF IN pin. The conver-
sion rate is determined by the externally-applied clock.
PRODUCT HIGHLIGHTS
1. High Throughput with Low Power Consumption. The
AD7470 offers 1.75 MSPS throughput and the AD7472
offers 1.5 MSPS throughput rates with 4 mW power
consumption.
2. Flexible Power/Throughput Rate Management. The conver-
sion rate is determined by an externally-applied clock allow-
ing the power to be reduced as the conversion rate is reduced.
The part also features an auto sleep mode to maximize power
efficiency at lower throughput rates.
3. No Pipeline Delay. The part features a standard successive-
approximation ADC with accurate control of the sampling
instant via a
CONVST
input and once off conversion
control.
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