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參數資料
| 型號： | HSP48212VC-40 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 數字信號處理外設 |
| 英文描述： | Digital Video Mixer |
| 中文描述： | 12-BIT, DSP-MIXER, PQFP64 |
| 封裝： | MQFP-64 |
| 文件頁數： | 1/9頁 |
| 文件大小： | 57K |
| 代理商： | HSP48212VC-40 |
1
File Number
3627.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright Intersil Corporation 1999
HSP48212
Digital Video Mixer
The Intersil HSP48212 is a 68 pin Digital Video Mixer IC
intended for use in multimedia and medical imaging
applications.
The HSP48212 allows the user to mix two video sources
based on a programmable weighting factor. After weighting
the input data signals, the Video Mixer simply adds the two
weighted signals mathematically. This results in the mixed
output, which is a weighted sum of the two sources.
The input and output interfaces are synchronous with respect
to the input clock, simplifying the user interface requirements.
Input Data (DINA, DINB), Mix Factor (M) and control signals
(RND, TCB) may be delayed relative to each other in order to
compensate for any misalignment that may have occurred
prior to entering the HSP48212. Each input’s delay may be
independently programmed up to seven clock cycles.
The output data may be rounded to 8, 10, 12, or 13-bits. The
enabling of data onto the output data bus is under the user’s
control via an output enable signal (OE).
Features
12-Bit Pixel Data
Two’s Complement or Unsigned Data
12-Bit Mix Factor
13-Bit Signed or Unsigned Three State Output
Overflow Detection and Output Saturation
Rounding to 8, 10, 12, or 13-Bits
Input and Output Pixel Data Synchronous to Clock
Programmable Pipeline Delay of up to 7 Clock Cycles for
Control of Misaligned Input Data
TTL Compatible Inputs/Outputs
DC to 40MHz Clock Rate
Applications
Video Summing (Frame Addition)
Video Mixing
Fade In/Out
Video Switching
High Speed Multiplying
Block Diagram
Ordering Information
PART NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG. NO.
HSP48212VC-40
0 to 70
64 Ld MQFP
Q64.14x14
HSP48212JC-40
0 to 70
68 Ld PLCC
N68.95
DINB0-11
1-M
DINA0-11
M
O
F
DOUT0-12
12
13
0-7
12
12
RND0-1
2
TCB
OE
Σ
DELAY
0-7
DELAY
0-7
DELAY
0-7
DELAY
0-7
DELAY
SHIFT
LEFT
DOUT = 2 x [DINA x M + DINB x (1-M)]
Data Sheet
May 1999
相關PDF資料 |
PDF描述 |
|---|---|
| HSP50210JI-52 | Digital Costas Loop |
| HSP50210JC-52 | Digital Costas Loop |
| HSP50216KI | Four-Channel Programmable Digital DownConverter |
| HSP50307SC | Burst QPSK Modulator |
| HSP50307EVAL1 | 2.0GHz to 2.7GHz DownConverter |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HSP48410 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Histogrammer/Accumulating Buffer |
| HSP48410 WAF | 制造商:Intersil Corporation 功能描述: |
| HSP48410 WAF | 制造商:Intersil Corporation 功能描述: |
| HSP48410/883 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Histogrammer/Accumulating Buffer |
| HSP48410_04 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Histogrammer/Accumulating Buffer |
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