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參數資料
| 型號： | HT24LC02 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 2K-Bit 2-Wire Serial Interface CMOS Serial EEPROM(2K位、2線接口、 CMOS串行EEPROM) |
| 中文描述： | 的2K位2線串行接口的CMOS串行EEPROM（2K位，2線接口，串行EEPROM中的CMOS） |
| 文件頁數： | 4/8頁 |
| 文件大小： | 94K |
| 代理商： | HT24LC02 |
HT24LC02
4
November 16, 2000
Functional Description
Serial clock (SCL)
The SCL input is used for positive edge clock
data into each EEPROM device and negative
edge clock data out of each device.
Serial data (SDA)
The SDA pin is bidirectional for serial data
transfer. The pin is open-drain driven and
may be wired-OR with any number of other
open-drain or open collector devices.
A0, A1, A2
The A2, A1 and A0 pins are device address in-
puts that are hard wired for the HT24LC02.
As many as eight 2K devices may be ad-
dressed on a single bus system (the device ad-
dressing is discussed in detail under the
Device Addressing section).
Write protect (WP)
The HT24LC02 has a write protect pin that
provides hardware data protection. The write
protect pin allows normal read/write opera-
tions when connected to the V
SS
. When the
writeprotectpinisconnectedtoVcc,thewrite
protection feature is enabled and operates as
shown in the following table.
WP Pin
Status
Protect Array
At V
CC
Full Array (2K)
At V
SS
Normal Read/Write Operations
Memory organization
HT24LC02, 2K Serial EEPROM
Internally organized with 256 8-bit words,
the2Krequiresan8-bitdatawordaddressfor
random word addressing.
Device operations
Clock and data transition
Data transfer may be initiated only when the
bus is not busy. During data transfer, the data
line must remain stable whenever the clock
line is high. Changes in data line while the
clock line is high will be interpreted as a
START or STOP condition.
Start condition
A high-to-low transition of SDA with SCL
high is a start condition which must precede
any other command (refer to Start and Stop
Definition Timing diagram).
Stop condition
A low-to-high transition of SDA with SCL
high is a stop condition. After a read se-
quence, the stop command will place the
EEPROM in a standby power mode (refer to
Start and Stop Definition Timing Diagram).
Acknowledge
All addresses and data words are serially
transmitted to and from the EEPROM in
8-bit words. The EEPROM sends a zero to ac-
knowledge that it has received each word.
This happens during the ninth clock cycle.
Device addressing
The 2K EEPROM devices all require an 8-bit
device address word following a start condition
to enable the chip for a read or write operation.
The device address word consist of a mandatory
one, zero sequence for the first four most signif-
icant bits (refer to the diagram showing the De-
vice Address). This is common to all the
EEPROM device.
The next three bits are the A2, A1 and A0 de-
vice address bits for the 2K EEPROM. These
three bits must compare to their corresponding
hard-wired input pins.
( ( ) ( !
) 0 (
! ! " " )
( 1 / !
2 (!
.
!
(
!
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相關代理商/技術參數 |
參數描述 |
|---|---|
| HT24LC02(8DIP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
| HT24LC02(8SOP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
| HT24LC02(8TSSOP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
| HT24LC02(SOP) | 制造商:Holtek Semiconductor Inc 功能描述:CMOS 2K 2-WIRE SERIAL EEPROM, SO8 |
| HT24LC02_10 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:CMOS 2K 2-Wire Serial EEPROM |
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