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參數(shù)資料
| 型號(hào)： | HT27LC040 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | CMOS 512K 8-Bit OTP EPROM |
| 中文描述： | 為512k的CMOS 8位檢察官辦公室存儲(chǔ)器 |
| 文件頁數(shù)： | 4/15頁 |
| 文件大?。?/td> | 175K |
| 代理商： | HT27LC040 |
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
CC
Conditions
Programming Operation
t
AS
Address Setup Time
6V
2
s
t
OES
OE Setup Time
6V
2
s
t
DS
Data Setup Time
6V
2
s
t
AH
Address Hold Time
6V
0
s
t
DH
Data Hold Time
6V
2
s
t
DFP
Output Enable to Output Float Delay
6V
0
130
ns
t
VPS
VPP Setup Time
6V
2
s
t
PW
CE Program Pulse Width
6V
30
75
105
s
t
VCS
VCC Setup Time
6V
2
s
t
CES
CE Setup Time
6V
2
s
t
OE
Data Valid from OE
6V
150
ns
t
PRT
VPPPulseRiseTimeDuringProgramming
6V
2
s
Test Waveforms and Measurements
Output Test Load
HT27LC040
Rev. 1.30
4
December 8, 2003
1 3 , "
$ 3 , 0 "
4
)
5
5 !
)
5
1 3 $ "
$ 3 + "
t
R
, t
F
< 20ns (10% to 90%)
* 3 - "
6 * 2 . * , 7
(
)
- 3 - 8
Note: C
L
=100pF including jig capacitance
Functional Description
Programming of the HT27LC040
When the HT27LC040 is delivered, the chip has all
4096K bits in the ONE , or HIGH state. ZEROs are
loaded into the HT27LC040 through programming.
The programming mode is entered when 12.5 0.2V is ap-
plied to the VPP pin, OE is at V
IH
, and CE is V
IL
. For pro-
gramming, the data to be programmed is applied with 8
bits in parallel to the data pins.
The programming flowchart in Figure 3 shows the fast
interactive programming algorithm. The interactive al-
gorithm reduces programming time by using 30 s to
105 s programming pulses and giving each address
only as many pulses as is necessary in order to reliably
program the data. After each pulse is applied to a given
address, the data in that address is verified. If the data
is not verified, additional pulses are given until it is veri-
fied or until the maximum number of pulses is reached
while sequencing through each address of the
HT27LC040. This process is repeated while sequenc-
ing through each address of the HT27LC040. This part
of the programming algorithm is done at V
CC
=6.0V to
assure that each EPROM bit is programmed to a suffi-
ciently high threshold voltage. This ensures that all bits
have sufficient margin. After the final address is com-
pleted, the entire EPROM memory is read at
V
CC
=V
PP
=3.3 0.3V to verify the entire memory.
Program Inhibit Mode
Programming of multiple HT27LC040 in parallel with dif-
ferent data is also easily accomplished by using the Pro-
gram Inhibit Mode. Except for CE, all like inputs of the
parallel HT27LC040 may be common. A TTL low-level
program pulse applied to an HT27LC040 CE input with
VPP=12.5 2V, and OE HIGH will program that
HT27LC040. A high-level CE input inhibits the
HT27LC040 from being programmed.
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