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參數資料
型號: HT48R10A-1
廠商: Holtek Semiconductor Inc.
英文描述: 8-Bit High Performance RISC-like Microcontroller Suitable for Multiple I/O Application(高性能、指令類似RISC的8位微控制器,用于多I/O接口設備)
中文描述: 8位高性能RISC架構微控制器等的多個I / O應用(高性能,指令類似的RISC的8位微控制器,用于多予適用/輸出接口設備)
文件頁數: 7/45頁
文件大小: 321K
代理商: HT48R10A-1
HT48R10A-1
7
November 29, 2000
Location 008H
This area is reserved for the timer/event coun-
ter interrupt service program. If a timer inter-
rupt results from a timer/event counter
overflow,andiftheinterruptisenabledandthe
stack is not full, the program begins execution
at location 008H.
Table location
Any location in the PROM space can be used
as look-up tables. The instructions "TABRDC
[m]" (the current page, 1 page=256 words)
and "TABRDL [m]" (the last page) transfer
the contents of the lower-order byte to the
specified data memory, and the higher-order
byte to TBLH (08H). Only the destination of
the lower-order byte in the table is
well-defined, the other bits of the table word
are transferred to the lower portion of TBLH,
and the remaining 2 bits are read as "0". The
Table Higher-order byte register (TBLH) is
read only. The table pointer (TBLP) is a
read/write register (07H), which indicates the
table location. Before accessing the table, the
location must be placed in TBLP. The TBLH
is read only and cannot be restored. If the
main routine and the ISR (Interrupt Service
Routine) both employ the table read instruc-
tion, the contents of the TBLH in the main
routine are likely to be changed by the table
read instruction used in the ISR. Errors can
occur. In other words, using the table read in-
struction in the main routine and the ISR si-
multaneously should be avoided. However, if
the table read instruction has to be applied in
both the main routine and the ISR, the inter-
rupt is supposed to be disabled prior to the ta-
ble read instruction. It will not be enabled
until the TBLH has been backed up. All table
relatedinstructionsrequiretwocyclestocom-
plete the operation. These areas may function
as normal program memory depending upon
the requirements.
Mode
Program Counter
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
External Interrupt
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter Overflow
0
0
0
0
0
0
1
0
0
0
Skip
PC+2
Loading PCL
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program counter
Note: *9~*0: Program counter bits
S9~S0: Stack register bits
#9~#0: Instruction code bits
@7~@0: PCL bits
= 1 / %
. >
6 6 >
. 6 6 >
# * + # ' ,
$ , * # 2
$ 1 & $. 1 / 1 ' ( 1 @ ' / 1 * . # * + # ' ,
9 / $ # . ' ( . / $ # # - 0 / - = # * - / 1 . $
1 , $ # $ . /* - . / $ # / $ # # - 0 /- = # * - / 1 . $
* * < : - 0 ' = ( $ 7A * # 3 % 8
* * < : - 0 ' = ( $ 7A * # 3 % 8
* / $ B # ' . + $ % ) # * , / *
>
>
>
Program memory
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