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參數資料
型號: HT49R50
廠商: Holtek Semiconductor Inc.
元件分類: 8位微控制器
英文描述: 8-BIT MICROCONTROLLER
中文描述: 8位微控制器
文件頁數: 17/59頁
文件大小: 339K
代理商: HT49R50
HT49R50
17
October 22, 1999
Watchdog timer
WDT
The WDT clock source is implemented by a ded-
icated RC oscillator (WDT oscillator) or an in-
struction clock (system clock/4) or a real time
clock oscillator (RTC oscillator). The timer is
designed to prevent a software malfunction or
sequence from jumping to an unknown location
with unpredictable results. The WDT can be
disabled by options. But if the WDT is disabled,
all executions related to the WDT lead to no op-
eration.
After the WDT clock source is selected, the
time-out period isf
S
/2
15
~f
S
/2
16
.
If the WDT clock source chooses the internal
WDT oscillator, the time-out period may vary
with temperature, VDD, and process variations.
On the other hand, if the clock source selects the
instruction clock and the halt instruction is ex-
ecuted, WDT may stop counting and lose its pro-
tecting purpose, and the logic can only be
restarted by an external logic.
When the device operates in a noisy environ-
ment, using the on-chip RC oscillator (WDT
OSC)isstronglyrecommended,sincetheHALT
can stop the system clock.
The WDT overflow under normal operation
initializes a "chip reset" and sets the status bit
"TO". In the HALT mode, the overflow
initializes a "warm reset", and only the PC and
SP are reset to zero. To clear the contents of the
WDT, there are three methods to be adopted,
i.e., external reset (a low level to RES), software
instruction, and a HALT
are two types of software instructions; "CLR
WDT" and the other set
"CLR WDT2". Of these two types of instruction,
only one type of instruction can be active at a
time depending on the options
times selection option . If the "CLR WDT" is se-
lected (i.e., CLR WDT times equal one), any ex-
ecution of the "CLR WDT" instruction clears
the WDT. In the case that "CLR WDT1" and
"CLR WDT2" are chosen (i.e., CLR WDT times
equaltwo),thesetwoinstructionshavetobeex-
ecuted to clear the WDT; otherwise, the WDT
may reset the chip due to time-out.
instruction. There
"CLR WDT1" and
"CLR WDT"
Multi-function timer
TheHT49R50providesamulti-functiontimerfor
the WDT, time base and RTC but with different
time-out periods. The multi-function timer con-
sists of a 7-stage divider and an 8-bit prescaler,
with the clock source coming from the WDT OSC
or RTC OSC or the instruction clock (i.e.., system
clock divided by 4). The multi-function timer also
provides a selectable frequency signal (ranges
from f
S
/2
2
to f
S
/2
8
) for LCD driver circuits, and a
selectable frequency signal (ranges from f
S
/2
2
to
f
S
/2
9
) for the buzzer output by options. It is rec-
ommended to select a near 4kHz signal to LCD
driver circuits for proper display.
! % < = ' -
<
.
% <
=
<
.
= > @
/ 1 3 4 > @
*
*
$
:%
$ '
2
+ $ '
3
Watchdog timer
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