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參數資料
| 型號： | HT82A822R_07 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | USB Audio MCU |
| 中文描述： | USB音頻控制器 |
| 文件頁數： | 7/39頁 |
| 文件大小： | 288K |
| 代理商： | HT82A822R_07 |
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HT82A822R
Rev. 1.10
7
June 29, 2007
gram counter is restored to its previous value from the
stack.Afterachipreset,theSPwillpointtothetopofthe
stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledge signal will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a CALL is sub-
sequently executed, stack overflow occurs and the first
entry will be lost (only the most recent 16 return ad-
dresses are stored).
Data Memory
RAM
The data memory (RAM) is designed with 192 8 bits.
The data memory is divided into two functional groups:
namely; special function registers 54 8 bits and general
purpose data memory, Bank0: 192 8 bits, Bank1~
Bank4: 128 8 4 bits (Read Only), Bank5~Bank8:
128 8 4 bits. Most are read/write, but some are read
only.
The special function registers include the indirect ad-
dressing registers (R0;00H, R1;02H), Bank register (BP,
04H), Timer/Event Counter 0 higher order byte register
(TMR0H;0CH), Timer/Event Counter 0 lower order byte
register (TMR0L;0DH), Timer/Event Counter 0 control
register (TMR0C;0EH), Timer/Event Counter 1 higher
order byte register (TMR1H;0FH), Timer/Event Counter
1 lower order byte register (TMR1L;10H), Timer/Event
Counter 1 control register (TMR1C;11H), program coun-
terlower-orderbyteregister(PCL;06H),memorypointer
registers (MP0;01H, MP1;03H), accumulator
(ACC;05H), table pointer (TBLP;07H, TBHP;1FH), table
higher-order byte register (TBLH;08H), status register
(STATUS;0AH),
interrupt
(INTC0;0BH), Watchdog Timer option setting register
(WDTS;09H), I/O registers (PA;12H), I/O control regis-
ters (PAC;13H). Digital Volume Control Register
(USVC;1CH). USB speaker flag register (USF;1DH),
USB status and control register (USC;20H), USB end-
point interrupt status register (USR;21H), system clock
control register (UCC;22H). Address and remote
wakeup register (AWR;23H), STALL register(24H),
SIES register (25H), MISC register(26H), SETIO regis-
ter(27H), FIFO0~FIFO2 register (28H~2AH).
DAC_Limit_L register (2DH), DAC_Limit_H register
(2EH), DAC_WR register (2FH).
control
register0
The remaining space before the 40H is reserved for fu-
ture expanded usage and reading these locations will
get
dressed from 40H to FFH, is used for data and control
information under instruction commands.
00H . The general purpose data memory, ad-
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations di-
rectly. Except for some dedicated bits, each bit in the
data memory can be set and reset by SET [m].i and
CLR [m].i . They are also indirectly accessible through
memory pointer registers (MP0 or MP1).
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RAM Mapping
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相關代理商/技術參數 |
參數描述 |
|---|---|
| HT82A824R | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:USB Audio MCU |
| HT82A832R | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:USB Audio MCU |
| HT82A832R_07 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:USB Audio MCU |
| HT82A834R | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:USB Audio MCU |
| HT82A836R | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:USB Audio MCU |
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