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參數(shù)資料
| 型號： | HT82K68E |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 8-Bit High Performance Peripheral Interface IC For Multiple I/O Products and Multimedia Applications(8位高性能外圍接口集成芯片，用于多I/O口及多媒體器件) |
| 中文描述： | 8位高性能外圍接口芯片為多個I / O產(chǎn)品和多媒體應(yīng)用（8位高性能外圍接口集成芯片，用于多的I / O口及多媒體器件） |
| 文件頁數(shù)： | 15/40頁 |
| 文件大小： | 257K |
| 代理商： | HT82K68E |
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HT82K68E
15
December 11, 2000
when the reset conditions are met. By examin-
ing the PD and TO flags, the program can dis-
tinguish between different chip resets .
TO
PD
RESET Conditions
0
0
RESET reset during power-up
u
u
RESET reset during normal
operation
0
1
RESET wake-up HALT
1
u
WDT time-out during normal
operation
1
1
WDT wake-up HALT
Note: u means unchanged
To guarantee that the system oscillator has
started and stabilized, the SST (System
Start-upTimer)providesanextra-delayof1024
system clock pulses when the system powers up
or when it awakes from the HALT state.
When a system power-up occurs, the SST delay
is added during the reset period. But when the
reset comes from the RESET pin, the SST delay
is disabled. Any wake-up from HALT will en-
able the SST delay.
The functional unit chip reset status is shown
below.
PC
000H
Prescaler
Clear
WDT
Clear. After master re-
set, WDT begins count-
ing
Timer counter
Off
Input/output ports Input mode
SP
Points to the top of
the stack
Timer counter
A timer counter (TMR) is implemented in the
HT82K68E. The timer counter contains an
8-bit programmable count-up counter and the
clock may come from the system clock divided
by 4.
Using the internal instruction clock, there is
only one reference time-base.
There are two registers related to the timer
counter; TMR ([0DH]), TMRC ([0EH]). Two
physical registers are mapped to TMR location;
writing TMR makes the starting value be
placedinthetimercounterpreloadregisterand
reading TMR gets the contents of the timer
counter. The TMRC is a timer counter control
register, which defines some options.
In the timer mode, once the timer counter
starts counting, it will count from the current
contents in the timer counter to FFH. Once
overflow occurs, the counter is reloaded from
the timer counter preload register and gener-
ates the interrupt request flag (TF; bit 5 of
INTC) at the same time.
Reset circuit
-
= ! #
-
:
.
@:&
:
&. &
-
&
Reset configuration
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