
HT82M99EE/HT82M99AE
Rev. 1.00
13
February 8, 2006
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
Therearefourwaysinwhicharesetcanoccur:
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
USB reset
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a warm re -
set thatresetsonlytheprogramcounterandSP,leaving
the other circuits in their original state. Some registers
remain unchanged during other reset conditions. Most
registers are reset to the initial condition when the re-
set conditions are met. By examining the PDF and TO
flags, the program can distinguish between different
chip resets .
TO PDF
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
Note: u stands for unchanged
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra delay of 1024 system clock pulses when the sys-
tem resets (power-up, WDT time-out or RES reset) or
the system awakes from the HALT state.
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will en-
able the SST delay.
The functional unit chip reset status are shown below.
Program Counter
000H
Interrupt
Disable
Prescaler
Clear
WDT
Clear. After master reset,
WDT begins counting
Timer/event Counter
Off
Input/output Ports
Input mode
Stack Pointer
Points to the top of the stack
Reset Circuit
+
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+
, #
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3 1 >
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Reset Configuration
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1
$
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Reset Timing Chart