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參數資料
| 型號： | HT82V26 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 16-Bit CCD/CIS Analog Signal Processor |
| 中文描述： | 16位防治荒漠化公約/獨聯體模擬信號處理器 |
| 文件頁數： | 4/16頁 |
| 文件大小： | 175K |
| 代理商： | HT82V26 |
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
DD
Conditions
Temperature Range
t
A
Operating
0
70
C
Power Consumption
P
tot
Total Power Consumption
400
mW
Timing Specification
Symbol
Parameter
Min.
Typ.
Max.
Unit
Clock Parameters
t
PRA
3-channel pixel rate
100
ns
t
PRB
2-channel (Even-Odd) pixel rate
66
ns
t
PRC
1-channel pixel rate
40
ns
t
ADCLK
ADCCLK Pulse Width
16
ns
t
C1
CDSCLK1 Pulse Width
12
ns
t
C2
CDSCLK2 Pulse Width
12
ns
t
C1C2
CDSCLK1 Falling to CDSCLK2 Rising
0
ns
t
ADC1
ADCCLK Rising to CDSCLK1 Falling
0
ns
t
ADC2
ADCCLK Rising to CDSCLK2 Falling
0
ns
t
AD
Analog Sampling Delay
5
ns
3-Channel Mode Only
ta
C2C1
CDSCLK2 Falling to CDSCLK1 Rising
30
ns
ta
C2ADR
CDSCLK2 Falling to ADCCLK Rising
30
ns
2-Channel Mode Only
tb
C2ADR
CDSCLK2 Falling to ADCCLK Rising
30
ns
tb
C1ADR
CDSCLK1 Rising to ADCCLK Rising
15
ns
tb
C2C1
CDSCLK2 Falling to CDSCLK1 Rising
15
ns
1-Channel Mode Only
tc
C2C1
CDSCLK2 Falling to CDSCLK1 Rising
15
ns
tc
C1ADF
CDSCLK1 Rising to ADCCLK Falling
0
ns
tc
C2ADR
CDSCLK2 Falling to CDSCLK1 Rising
20
ns
Serial Interface
f
SCLK
Maximum SCLK Frequency
10
MHz
t
LS
SLOAD to SCLK Setup Time
10
ns
t
LH
SCLK to SLOAD Hold Time
10
ns
t
DS
SDATA to SCLK Rising Setup Time
10
ns
t
DH
SCLK Rising to SDATA Hold Time
10
ns
t
RDV
Falling to SDATA Valid
10
ns
Data Output
t
OD
Output Delay
8
ns
Latency (Pipeline Delay)
9
Cycles
HT82V26
Rev. 1.50
4
June 24, 2004
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相關代理商/技術參數 |
參數描述 |
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| HT82V36 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:16-Bit CCD/CIS Analog Signal Processor |
| HT82V38 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:16-Bit CCD/CIS Analog Signal Processor |
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| HT82V42_10 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:Single-channel 16-Bit CCD/CIS Analog Signal Processor |
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