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參數資料
| 型號： | HT82V842 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | CCD CDS/PGA/10b-20M-ADC |
| 中文描述： | 防治荒漠化公約CDS/PGA/10b-20M-ADC |
| 文件頁數： | 12/18頁 |
| 文件大小： | 161K |
| 代理商： | HT82V842 |
AD Conversion Timing (at ADIN (ADC) Input Mode 1 Register D5=1)
These figures are shown when the Mode 1 D8 bit is set to 1 , and an external clock is input to the OUTCK pin. When
setting D8 bit to 0 , the ADCK is used as OUTCK.
Note:
At default condition in ADIN mode, data are sampled at the falling edge of the ADCK clock, and are output at
the rising edge of the OUTCK clock. Set the ADCK polarity register to 1 when the data are sampled and are
output at the falling edge of the ADCK clock.
The diagram on the upper portion of this page shows the default timing and the lower left figure shows the in-
verted timing.
Delay from data sampling to data output
ADCK normal: At Mode 1 register D6=0; 5.5 clk delay
ADCK inversion: At Mode 1 register D6=1; 6.0 clk delay
In ADIN input mode, the above mentioned register setting is available.
At ADIN (PGA) input Mode 1 register D5=0 and D4=1, digital data output is delayed by 2 clks.
ADCK Clock Waveform
HT82V842
Rev. 1.00
12
July 15, 2004
& - /
5
& - 7
5
& - /
5
& - 7
5
> %
> .
> 8
> (
' )
' %
"
4
"
"
' (
' 8
ADC Direct Input Chart
"
> %
ADCK Inversion Chart
4
4
OUTCK Timing Chart
& - / 5
& - 7 5
6
相關PDF資料 |
PDF描述 |
|---|---|
| HT82V842-48LQFP-A | CCD CDS/PGA/10b-20M-ADC |
| HT83R074 | Q-Voice |
| HT84036 | Magic VoiceTM |
| HT84XXX | Magic VoiceTM |
| HT84072 | Magic VoiceTM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HT82V842-48LQFP-A | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:CCD CDS/PGA/10b-20M-ADC |
| HT82V842A | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:10-Bit 20MSPS CCD Analog Signal Processor |
| HT82V863R | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:CCD Digital Signal Processor |
| HT83 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Common Mode Chokes for High Speed Telecommunications |
| HT83-00007 | 制造商:BITECH 制造商全稱:Bi technologies 功能描述:T1/CEPT/ISDN-Pri Telecom Products |
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