
HT95CXXX
Rev. 1.50
23
May 26, 2005
Some input/output pins can be optioned to LCD outputs by software.
Bit No.
Label
R/W
Value
400/40P
300/30P
200/20P
5
SPE0
RW
0
SEG47~SEG44
1
PE3~PE0
7
SPD1
RW
0
SEG43~SEG40
1
PD7~PD4
6
SPD0
RW
0
SEG39~SEG36
1
PD3~PD0
1
VBIAS
RW
0
COM7~COM0
COM7~COM0
1
COM7~COM0 are unavailable
PD7~PD0
LCDIO (28H) Register
Bit No.
Label
R/W
Value
400/40P
300/30P
200/20P
1
VBIAS
RW
0
COM7~COM0
COM7~COM0
1
COM7~COM0 are unavailable
PD7~PD0
LCDC (2DH) Register
6
/ / " 1
"
" .
0
"
" $ 4 )
" .
0
<
"
/ =
"
"
D
9
D 7
D
9
D 7
/ " 7
" 7
.
"
/ "
"
"
/ "
.
"
"
" 7
Input/Output Ports
When the PD0~PD7 or the PE0~PE3 are not selected,
the I/O port control register PDC(19H), PEC(1BH) could
be readable/writable and be used as a general user
RAM, but this function is not available for register PD
(18H) and PE (1AH).
FSK Decoder
The FSK decoder supports three interrupt sources to
the peripheral interrupt vector. There are ring detect or
line reversal detect, FSK carrier detect and FSK packet
data. Write 0 to the control flag, RMSK, CMSK and
FMSK will enable these interrupt. When any of these in-
terrupt occurs, its interrupt flag (RDETF, CDETF, FSKF)
will be set to 1 by hardware even if the interrupt is dis-
abled. These interrupts will cause a peripheral interrupt
if the peripheral interrupt is enabled.When the periph-
eral interrupt occurs, the interrupt request flag PERF will
be set and a subroutine call to location 10H will occur.
Returning from the interrupt subroutine, the interrupt
flag RDETF, CDETF or FSKF will not be cleared by
hardware, the user should clear it by software. If inter-
rupt flag RDETF is not cleared, next ring detect interrupt
will be inhibited, other interrupt flags CDETF, FSKF
have the same behavior. The power down mode
(F_PWDN=1) will terminate all the FSK decoder func-
tion, however, the registers FSKC, FSKS and FSKD are
accessible at this power down mode.