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參數資料
| 型號： | HV219X |
| 廠商： | SUPERTEX INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | Low Charge Injection 8-Channel High Voltage Analog Switch |
| 中文描述： | 1-CHANNEL, SGL ENDED MULTIPLEXER, UUC |
| 封裝： | DIE |
| 文件頁數： | 5/8頁 |
| 文件大小： | 572K |
| 代理商： | HV219X |
HV219
A042705
5
Power Up/Down Sequence
1)
Power up/down sequence is arbitrary except GND must be powered up first and powered down last. This applies for
applications powering GND of the IC with different voltages.
2)
Vsig must always be at or in between V
PP
and V
NN
or floating during power up/down transition.
3)
Rise and fall times of the power supplies V
DD
, V
PP
, and V
NN
should not be less than 1.0ms.
Logic Truth Table
Data in the 8-bit Shift Register
D0
D1
D2
D3
D4
D5
D6
D7
SW0
L
L
L
OFF
H
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
H
L
L
X
X
X
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
H
OFF
Notes:
1.
The eight switches operate independently.
2.
Serial data is clocked in on the L to H transition clock.
3.
The switches go to a state retaining their present condition at the rising edge of the
LE
.
Output Switch State
SW2
SW3
OFF
ON
OFF
ON
HOLD PREVIOUS STATE
OFF
OFF
LE
CL
SW1
OFF
ON
SW4
OFF
ON
SW5
OFF
ON
SW6
OFF
ON
SW7
OFF
ON
ON
OFF
OFF
OFF
OFF
OFF
4.
When
LE
is low, the shift register data flows through the latch.
5.
6.
Shift register clocking has no effect on the switch states if
LE
is high.
The clear input overrides all other inputs.
Logic Timing Waveform
DATA
IN
LE
CLOCK
DATA
OUT
D
N - 1
N
N + 1
D
D
50%
50%
50%
50%
50%
50%
50%
50%
50%
(TYP)
V OFF
ON
CLR
t
WCL
90%
10%
tOFF
DD
SD
ON
t
t
t
t
t
h
WLE
SU
t
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