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參數資料
| 型號： | HW3100 |
| 廠商： | Lineage Power |
| 英文描述： | Home Phoneline Networking Chip Set(主電話線網絡物理層) |
| 中文描述： | 家庭電話線網絡芯片組（主電話線網絡物理層） |
| 文件頁數： | 1/6頁 |
| 文件大小： | 144K |
| 代理商： | HW3100 |
Preliminary Product Brief
August 2000
HW3100/HW2000 Home Wire
TM
Home Phoneline
Networking Chip Set
Chip Set Features
I
Turnkey solution for PCI adapter cards
I
Support for the HomePNA* Interface Specification
2.0:
— Adaptive rate selection: 1 Mbit/s to 16 Mbits/s
I
Compliant with HomePNA PHY Specification Revi-
sion 1.1:
— Integrated 1 Mbit/s PHY on the HW3100
— Automatically selects between HomePNA1.1/
2.0 modulation and protocol based on capabili-
ties of partner station on the network
I
Highly integrated home phoneline networking chip
set with an IEEE
802.3-compliant 10/100 Mbits/s
media access controller (MAC):
— HW3100 HomePNAmodem controller
— HW2000 analog front end (AFE)
I
Support for multimedia and real-time applications
using priority-based queuing quality of service
(QoS):
— Implements eight levels of packet priority
I
Compatible with existing services:
— Voice
— V.90 and emerging V.92 analog modems
— G.Lite splitterless DSL (G.992.2)
— Full-rate DSL (G.992.1)
— ISDN
I
Highly integrated HW2000 AFE:
— Support for all HomePNA 2.0 front-end transmit
and receive operations
— Minimal additional components required
— 10-bit ADC and DAC
— Integrated crystal oscillator: 28 MHz fundamen-
tal mode crystal
— On-chip filtering
I
IEEE
802.3 (Ethernet)-compliant media access
controller (MAC):
— Address filtering: unicast, multicast, broadcast,
and promiscuous mode
— Tx and Rx packet status information
I
Bus mastering architecture with integrated Tx and
Rx direct memory access (DMA) controllers and
buffer management for efficient CPU utilization
I
Independent transmit and receive FIFOs with pro-
grammable thresholds
— Buffer can accommodate 3.5 maximum size
Ethernet packets
— User-programmable Tx and Rx buffer sizes
I
Low-power, 3.3 V, 0.20 μm technology
PCI Features
I
Glueless peripheral component interconnect (PCI)
interfaces:
— 5.0 V and 3.3 V signaling
I
Compliant with PCI Bus Specification, Revision 2.2
Power Management Features
I
Compliant with the Network Device Class Power
Management Specification, Revision 1.0a, as
defined in the PC99 Hardware Design Guide
I
Compliant with PCI Bus Power Management Inter-
face Specification, Revision 1.1
I
Supports the Advanced Configuration and Power
Interface (ACPI) Specification, Revision 1.0
* HomePNA s an acronym for Home Phoneline Networking Alli-
ance. It is a trademark of HomePNA, Inc.
IEEEis a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
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