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參數資料
| 型號： | HX6218DSRT |
| 英文描述： | x18 Synchronous FIFO |
| 中文描述： | x18同步FIFO |
| 文件頁數： | 1/16頁 |
| 文件大?。?/td> | 156K |
| 代理商： | HX6218DSRT |
FIFO—SOI
HX6409
HX6218
HX6136
Aerospace Electronics
FEATURES
1K x 36, 2K x 18, 4K x 9 Organizations
Fabricated with RICMOS
IV Silicon on Insulator
(SOI) 0.8
μ
m Process (L
eff
= 0.65
μ
m)
RADIATION
Total Dose Hardness through 1x10
6
rad(SiO
2
)
Neutron Hardness through 1x10
14
cm
-2
Dynamic and Static Transient Upset Hardness
through 1x10
9
rad(Si)/s
Dose Rate Survivability through 1x10
11
rad(Si)/s
Soft Error Rate of <1x10
-10
upsets/bit-day
No Latchup
OTHER
Read/Write Cycle Times
<35 ns (-55
°
to 125
°
C)
Expandable in Width
Supports Free-Running 50% Duty Cycle Clock
Empty, Full, Half Full, 1/4 Full, 3/4 Full, Error Flags
Parity Generation/Checking
Fully Asynchronous with Simultaneous
Read and Write Operation
Output Enable (OE)
CMOS or TTL Compatible I/O
Single 5 V
±
10% Power Supply
Various Flat Pack Options
The HX6409, HX6218, and HX6136 are high speed, low-
power, first-in first-out memories with clocked read and
write interfaces. The HX6409 is a 4096 word by 9 bit
memory array, the HX6218 is a 2048 word by 18 bit
memory array, and the HX6136 is a 1024 word by 36 bit
memory array. The FIFOs support width expansion while
depth expansion requires external logic control using state
machine techniques. Features include programmable par-
ity control, an empty/full flag, a quarter/three quarter full
flag, a half full flag and an error flag.
These FIFOs provide solutions for a wide variety of data
buffering needs, including high-speed data acquisition,
multiprocessor interfaces, and communications buffer-
ing. These FIFOs have separate input and output ports
that are controlled by separate clock and enable sig-
nals. The input port is controlled by a free running clock
(CKW) and a write enable pin
ENW
. When
ENW
is
asserted, data is written into the FIFO on the rising edge
of the CKW signal. While
ENW
is held active, data is
continually written into the FIFO on each CKW cycle.
The output port is controlled in a similar manner by a free-
running read clock (CKR) and a read enable pin (
ENR
). In
addition, the three FIFOs have an output enable pin (
OE
)
and a master reset pin (
MR
). The read (CKR) and write
(CKW) clocks may be tied together for single-clock
operation or the two clocks may be run independently for
asynchronous read/write applications. Clock frequencies
up to 30 MHz are achievable in the three configurations.
Honeywell’s enhanced SOI RICMOS
IV (Radiation In-
sensitive CMOS) technology is radiation hardened through
the use of advanced and proprietary design, layout and
process hardening techniques. The FIFO is fabricated with
Honeywell’s radiation hardened technology, and is de-
signed for use in systems operating in radiation environ-
ments. The SOI RICMOS IV process is a 5-volt, SIMOX
CMOS technology with a 150 gate oxide and a minimum
drawn feature size of 0.8
μ
m, (0.65
μ
m effective gate
array—L
). Additional features include tungsten via plugs,
Honeywell’s proprietary SHARP planarization process,
and a lightly doped drain (LDD) structure for improved short
channel reliability.
GENERAL DESCRIPTION
Solid State Electronics Center 12001 State Highway 55, Plymouth, MN 55441 (800) 323-8295 http://www.ssec.honeywell.com
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|---|---|
| HX6409TSHT | x9 Synchronous FIFO |
| HX6409TSNC | x9 Synchronous FIFO |
| HX6409TSNT | x9 Synchronous FIFO |
| HX6409TSRC | x9 Synchronous FIFO |
| HX6409TSRT | x9 Synchronous FIFO |
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| HX6218DVFC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
| HX6218DVFT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
| HX6218DVHC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
| HX6218DVHT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
| HX6218DVNC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
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