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參數資料
| 型號： | HY27SA1G1M |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory |
| 中文描述： | 1Gbit的（128Mx8bit / 64Mx16bit）NAND閃存 |
| 文件頁數： | 8/43頁 |
| 文件大小： | 729K |
| 代理商： | HY27SA1G1M |
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Rev 0.5 / Oct. 2004
8
HY27UA(08/16)1G1M Series
HY27SA(08/16)1G1M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
SIGNAL DESCRIPTIONS
See Figure 1, Logic Diagram and Table 1, Signal Names, for a brief overview of the signals connected to this device.
Inputs/Outputs (I/O
0
-I/O
7
)
Input/Outputs 0 to 7 are used to input the selected address, output the data during a Read opertion or input a com-
mand or data during a Write operation. The inputs are latched on the rising edge of Write Enable. I/O
0
-I/O
7
can be left
floating when the device is deselected or the outputs are disabled.
Inputs/Outputs (I/O
8
-I/O
15
)
Input/Outputs 8 to 15 are only available in x16 devices. They are used to output the data during a Read operation or
input data during a Write operation. Command and Address Inputs only require I/O
0
to I/O
7
.
The inputs are latched on the rising edge of Write Enable. I/O
8
-I/O
15
can be left floating when the device is deselected
or the outputs are disabled.
Address Latch Enable (ALE)
The Address Latch Enable activates the latching of the Address inputs in the Command Interface. When ALE is high,
the inputs are latched on the rising edge of Write Enable.
Command Latch Enable (CLE)
The Command Latch Enable activates the latching of the Command inputs in the Command Interface. When CLE is
high, the inputs are latched on the rising edge of Write Enable.
Chip Enable (CE)
The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip En-
able is low, V
IL
, the device is selected. If Chip Enable goes high, V
IH
, while the device is busy, the device remains se-
lected and does not go into standby mode.
When the device is executing a Sequential Row Read operation, Chip Enable must be held low (from the second page
read onwards) during the time that the device is busy (t
BLBH1
). If Chip Enable goes high during t
BLBH1
the operation is
aborted.
Read Enable (RE)
The Read Enable, RE, controls the sequential data output during Read operations. Data is valid t
RLQV
after the falling
edge of RE. The falling edge of RE also increments the internal column address counter by one.
Write Enable (WE).
The Write Enable input, WE, controls writing to the Command Interface, Input Address and Data
latches. Both addresses and data are latched on the rising edge of Write Enable.
During power-up and power-down a recovery time of 1us (min) is required before the Command Interface is ready to
accept a command. It is recommended to keep Write Enable high during the recovery time.
Write Protect (WP).
The Write Protect pin is an input that gives a hardware protection against unwanted program or erase operations.
When Write Protect is Low, V
IL
, the device does not accept any program or erase operations.
It is recommended to keep the Write Protect pin Low, V
IL
, during power-up and power-down.
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