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參數(shù)資料
| 型號： | HY57V161610ETP-I |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | 2 Banks x 512K x 16 Bit Synchronous DRAM |
| 中文描述： | 2銀行x為512k × 16位同步DRAM |
| 文件頁數(shù)： | 1/11頁 |
| 文件大小： | 574K |
| 代理商： | HY57V161610ETP-I |
HY57V161610D-I
2 Banks x 512K x 16 Bit Synchronous DRAM
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied
Rev. 0.3/Mar. 02 1
DESCRIPTION
THE Hynix HY57V161610D is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the Mobile applications
which require low power consumption and industrial temperature range. HY57V161610D is organized as 2banks of
524,288x16.
HY57V161610D is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are
synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high band-
width. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of consecutive read or
write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipeline
design is not restricted by a `2N` rule.)
FEATURES
Single 3.0V to 3.6V power supply
Note1)
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 50pin TSOP-II with 0.8mm
of pin pitch
All inputs and outputs referenced to positive edge of
system clock
Data mask function by UDQM/LDQM
Internal two banks operation
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 and Full Page for Sequence Burst
- 1, 2, 4 and 8 for Interleave Burst
Programmable CAS Latency ; 1, 2, 3 Clocks
ORDERING INFORMATION
Part No.
Clock Frequency
Organization
Interface
Package
HY57V161610DTC-55I
183MHz
2Banks x 512Kbits x 16
LVTTL
400mil
50pin TSOP II
HY57V161610DTC-6I
166MHz
HY57V161610DTC-7I
143MHz
HY57V161610DTC-10I
100MHz
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY57V161610DTC-10 | 2 Banks x 512K x 16 Bit Synchronous DRAM |
| HY57V161610DTC-15 | 2 Banks x 512K x 16 Bit Synchronous DRAM |
| HY57V161610D | 2 Banks x 512K x 16 Bit Synchronous DRAM |
| HY57V161610DTC-5 | 2 Banks x 512K x 16 Bit Synchronous DRAM |
| HY57V161610DTC-55 | 2 Banks x 512K x 16 Bit Synchronous DRAM |
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| HY57V16161TC-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
| HY57V16161TC-13 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
| HY57V16161TC-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
| HY57V164010ALTC-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SDRAM |
| HY57V164010ALTC-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SDRAM |
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