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參數資料
| 型號： | HY57V283220T |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | 4 Banks x 1M x 32Bit Synchronous DRAM |
| 中文描述： | 4銀行× 1米x 32Bit的同步DRAM |
| 文件頁數： | 1/15頁 |
| 文件大小： | 913K |
| 代理商： | HY57V283220T |
HY57V283220(L)T(P)/ HY5V22(L)F(P)
4 Banks x 1M x 32Bit Synchronous DRAM
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.9 / July 2004
Revision History
Revision No.
History
Remark
0.1
Defined Preliminary Specification
0.2
1) Modified FBGA Ball Configuration Typo.
2) Changed Functional Block Diagram from A10 to A11.
3) Changed V
DD
min from 3.0V to 3.135V.
4) Changed Cap. Value from C11, 3, 5 to 4pf & C12, 3.8 to 4pf.
5) Insert t
AC2
Value.
6) Insdrt t
RAS
& CLK Value.
0.3
Defined I
DD
Spec.
0.4
Delited Preliminary.
0.5
Changed I
DD
Spec.
0.6
133MHz Speed Added
0.7
Changed FBGA Package Size from 11x13 to 8x13.
0.8
1) Changed V
DD
min from 3.135V to 3.0V.
2) Changed V
IL
min from V
SSQ
-0.3V to -0.3V.
0.9
Modified of size erra. (Page15)
(Equation :
13.00
±
10
-> 13.00
±
0.10)
相關PDF資料 |
PDF描述 |
|---|---|
| HY57V283220(L)T(P)-5 | 4 Banks x 1M x 32Bit Synchronous DRAM |
| HY57V283220(L)T(P)-55 | 4 Banks x 1M x 32Bit Synchronous DRAM |
| HY57V283220(L)T(P)-6 | 4 Banks x 1M x 32Bit Synchronous DRAM |
| HY57V283220(L)T(P)-7 | 4 Banks x 1M x 32Bit Synchronous DRAM |
| HY57V283220(L)T(P)-8 | 4 Banks x 1M x 32Bit Synchronous DRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HY57V283220T-5 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 1M x 32Bit Synchronous DRAM |
| HY57V283220T-55 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 1M x 32Bit Synchronous DRAM |
| HY57V283220T-6 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 1M x 32Bit Synchronous DRAM |
| HY57V283220T-7 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 1M x 32Bit Synchronous DRAM |
| HY57V283220T-8 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 1M x 32Bit Synchronous DRAM |
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