欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數資料
型號: HY57V56420T-P
英文描述: x4 SDRAM
中文描述: x4內存
文件頁數: 1/13頁
文件大小: 61K
代理商: HY57V56420T-P
HY57V281620A
4 Banks x 2M x 16bits Synchronous DRAM
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits de-
scribed. No patent licenses are implied.
Rev. 1.3/Aug. 01
DESCRIPTION
The Hynix HY57V281620A is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. HY57V281620A is organized as 4banks of 2,097,152x16
HY57V281620A is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8, or full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
Single 3.3
±
0.3V power supply
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
All inputs and outputs referenced to positive edge of
system clock
Data mask function by UDQM or LDQM
Internal four banks operation
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No.
Clock Frequency
Power
Organization
Interface
Package
HY57V281620AT-6
166MHz
Normal
4Banks x 2Mbits
x16
LVTTL
400mil 54pin TSOP II
HY57V281620AT-7
143MHz
HY57V281620AT-K
133MHz
HY57V281620AT-H
133MHz
HY57V281620AT-8
125MHz
HY57V281620AT-P
100MHz
HY57V281620AT-S
100MHz
HY57V281620ALT-6
166MHz
Low power
HY57V281620ALT-7
143MHz
HY57V281620ALT-K
133MHz
HY57V281620ALT-H
133MHz
HY57V281620ALT-8
125MHz
HY57V281620ALT-P
100MHz
HY57V281620ALT-S
100MHz
相關PDF資料
PDF描述
HY57V56420T-S x4 SDRAM
HY57V56820ALT-10 x8 SDRAM
HY57V56820ALT-6 x8 SDRAM
HY57V56820ALT-8 x8 SDRAM
HY57V56820ALT-H x8 SDRAM
相關代理商/技術參數
參數描述
HY57V56420T-S 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SDRAM
HY57V56820ALT-10 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM
HY57V56820ALT-6 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM
HY57V56820ALT-8 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM
HY57V56820ALT-H 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM
主站蜘蛛池模板: 丹江口市| 西丰县| 沧州市| 全椒县| 舒城县| 缙云县| 博湖县| 汉川市| 柳林县| 唐山市| 澄迈县| 汉沽区| 嘉祥县| 三台县| 乃东县| 隆林| 敦化市| 醴陵市| 耒阳市| 宁津县| 桂林市| 樟树市| 交口县| 安塞县| 霍城县| 巫山县| 安阳市| 安陆市| 沂水县| 丰台区| 石嘴山市| 习水县| 锡林郭勒盟| 通城县| 新民市| 高青县| 礼泉县| 绍兴市| 远安县| 水城县| 宁明县|