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參數資料
| 型號： | HY57V56820CLT-H |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 4 Banks x 8M x 8Bit Synchronous DRAM |
| 中文描述： | 32M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.875 X 0.400 INCH, 0.80 MM PITCH, TSOP2-54 |
| 文件頁數： | 1/12頁 |
| 文件大小： | 89K |
| 代理商： | HY57V56820CLT-H |
HY57V56820C(L)T
4 Banks x 8M x 8Bit Synchronous DRAM
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 0.4 / July 2003 1
DESCRIPTION
The HY57V56820C is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large
memory density and high bandwidth. The HY57V56820C is organized as 4banks of 8,388,608x8.
The HY57V56820C is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by
a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or
write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or
write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
Single 3.3
±
0.3V power supply
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin
pitch
All inputs and outputs referenced to positive edge of system
clock
Data mask function by DQM
Internal four banks operation
Auto refresh and self refresh
8192 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No.
Clock Frequency
Power
Organization
Interface
Package
HY57V56820CT-6
166MHz
Normal
4Banks x 8Mbits x8
LVTTL
400mil 54pin TSOP II
HY57V56820CT-K
133MHz
HY57V56820CT-H
133MHz
HY57V56820CT-8
125MHz
HY57V56820CT-P
100MHz
HY57V56820CT-S
100MHz
HY57V56820CLT-6
166MHz
Low power
HY57V56820CLT-K
133MHz
HY57V56820CLT-H
133MHz
HY57V56820CLT-8
125MHz
HY57V56820CLT-P
100MHz
HY57V56820CLT-S
100MHz
相關PDF資料 |
PDF描述 |
|---|---|
| HY57V56820CLT-K | 4 Banks x 8M x 8Bit Synchronous DRAM |
| HY57V56820CLT-P | 4 Banks x 8M x 8Bit Synchronous DRAM |
| HY57V56820CLT-S | 4 Banks x 8M x 8Bit Synchronous DRAM |
| HY57V56820CT-6 | 4 Banks x 8M x 8Bit Synchronous DRAM |
| HY57V56820CT-8 | 4 Banks x 8M x 8Bit Synchronous DRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HY57V56820CLT-K | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 8M x 8Bit Synchronous DRAM |
| HY57V56820CLT-P | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 8M x 8Bit Synchronous DRAM |
| HY57V56820CLT-S | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 8M x 8Bit Synchronous DRAM |
| HY57V56820CT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32Mx8|3.3V|8K|6/K/H/8/P/S|SDR SDRAM - 256M |
| HY57V56820CT-6 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 8M x 8Bit Synchronous DRAM |
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