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參數資料
| 型號： | HY57W2A1620HCLT-B |
| 英文描述： | x16 SDRAM |
| 中文描述： | x16內存 |
| 文件頁數： | 1/24頁 |
| 文件大小： | 221K |
| 代理商： | HY57W2A1620HCLT-B |
HY5W2A6C(L/S)F / HY57W2A1620HC(L/S)T
HY5W26CF / HY57W281620HCT
4Banks x 2M x 16bits Synchronous DRAM
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 1.2 / Nov. 01
DESCRIPTION
The Hynix Low Power SDRAM is suited for non-PC application which use the batteries such as PDAs,
2.5G and 3G cellular phones with internet access and multimedia capabilities, mini-notebook, handheld
PCs.
The Hynix HY5W2A6CF is a 134,217,728bit CMOS Synchronous Dynamic Random Access Memory. It
is organized as 4banks of 2,097,152x16.
The Low Power SDRAM provides for programmable options including CAS latency of 1, 2, or 3, READ
or WRITE burst length of 1, 2, 4, 8, or full page, and the burst count sequence(sequential or interleave).
And the Low Power SDRAM also provides for special programmable options including Partial Array Self
Refresh of a quarter bank, a half bank, 1bank, 2banks, or all banks, Temperature Compensated Self
Refresh of 15, 45, 70, or 85 degrees C. A burst of Read or Write cycles in progress can be terminated
by a burst terminate command or can be interrupted and replaced by a new burst Read or Write com-
mand on any cycle(This pipelined design is not restricted by a 2N rule).
Deep Power Down Mode is a additional operating mode for Low Power SDRAM. This mode can achieve
maximum power reduction by removing power to the memory array within each SDRAM. By using this
feature, the system can cut off alomost all DRAM power without adding the cost of a power switch and
giving up mother-board power-line layout flexibility.
FEATURES
Standard SDRAM Protocol
Internal 4bank operation
Voltage : VDD = 2.5V, VDDQ = 1.8V
& 2.5
V
LVTTL compatible I/O Interface
Low Voltage interface to reduce I/O power
Low Power Features ( HY5W26CF / HY57W281620HCT series can’t support these features)
- PASR(Partial Array Self Refresh)
- TCSR(Temperature Compensated Self Refresh)
- Deep Power Down Mode
CAS latency of 1, 2, or 3
Packages : 54ball, 0.8mm pitch FBGA / 54pin, TSOP
-25 ~ 85C Operation
128M SDRAM ODERING INFORMATION
Part Number
Clock
Frequency
CAS
Latency
Organization
Interface
Package
HY5W2A6C(L/S)F-H
HY5W26CF-H
HY57W2A1620HC(L/S)T-H
HY57W281620HCT-H
133MHz
3
4banks x 2Mb x 16
LVTTL
54ball FBGA
(HY5xxxxxxF)
54pin TSOP-II
(HY5xxxxxxT)
HY5W2A6C(L/S)F-P
HY5W26CF-P
HY57W2A1620HC(L/S)T-P
HY57W281620HCT-P
100MHz
2
4banks x 2Mb x 16
LVTTL
HY5W2A6C(L/S)F-S
HY5W26CF-S
HY57W2A1620HC(L/S)T-S
HY57W281620HCT-S
100MHz
3
4banks x 2Mb x 16
LVTTL
HHY5W2A6C(L/S)F-B
HY5W26CF-B
HY57W2A1620HC(L/S)T-B
HY57W281620HCT-B
66Mhz
2
4banks x 2Mb x 16
LVTTL
* HY5xxxxxx-B Series can support 40Mhz CL1 and 33Mhz CL1.
相關PDF資料 |
PDF描述 |
|---|---|
| HY57W2A1620HCLT-H | SDRAM|4X2MX16|CMOS|TSOP|54PIN|PLASTIC |
| HY57W2A1620HCLT-P | x16 SDRAM |
| HY57W2A1620HCLT-S | SDRAM|4X2MX16|CMOS|TSOP|54PIN|PLASTIC |
| HY57W2A1620HCST-B | x16 SDRAM |
| HY57W2A1620HCST-H | SDRAM|4X2MX16|CMOS|TSOP|54PIN|PLASTIC |
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