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參數(shù)資料
| 型號(hào)： | HY5V26CLF-6I |
| 英文描述： | x16 SDRAM |
| 中文描述： | x16內(nèi)存 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大小： | 72K |
| 代理商： | HY5V26CLF-6I |
HY5V26C(L/S)F
4 Banks x 2M x 16bits Synchronous DRAM
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits de-
scribed. No patent licenses are implied.
Rev. 0.9/Oct. 01
DESCRIPTION
The Hynix HY5V26C(L/S)F is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the consumer memory applications
which require low power consumption and small form factor. HY5V26C(L/S)F is organized as 4banks of 2,097,152x16
HY5V26C(L/S)F is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8, or full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
Single 3.3
±
0.3V power supply
All device balls are compatible with LVTTL interface
54Ball FBGA (10.5mm x 8.3mm)
All inputs and outputs referenced to positive edge of
system clock
Data mask function by UDQM or LDQM
Internal four banks operation
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No.
Clock Frequency
Power
Organization
Interface
Package
HY5V26CF-6
166MHz
Normal
4Banks x 2Mbits
x16
LVTTL
54ball FBGA
HY5V26CF-K
133MHz
HY5V26CF-H
133MHz
HY5V26CF-8
125MHz
HY5V26CF-P
100MHz
HY5V26CF-S
100MHz
HY5V26C(L/S)F-6
166MHz
Low power
HY5V26C(L/S)F-K
133MHz
HY5V26C(L/S)F-H
133MHz
HY5V26C(L/S)F-8
125MHz
HY5V26C(L/S)F-P
100MHz
HY5V26C(L/S)F-S
100MHz
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY5V26CLF-8 | x16 SDRAM |
| HY5V26CLF-8I | x16 SDRAM |
| HY5V26CLF-H | x16 SDRAM |
| HY5V26CLF-HI | x16 SDRAM |
| HY5V26CLF-K | x16 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY5V26CLF-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
| HY5V26CLF-8I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
| HY5V26CLF-H | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 2M x 16bits Synchronous DRAM |
| HY5V26CLF-HI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
| HY5V26CLF-K | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 2M x 16bits Synchronous DRAM |
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