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參數資料
| 型號： | HY62256AR1-70 |
| 英文描述： | x8 SRAM |
| 中文描述： | x8的SRAM |
| 文件頁數： | 1/9頁 |
| 文件大小： | 144K |
| 代理商： | HY62256AR1-70 |
This document is a general product description and is subject to change without notice. Hyundai Electronics does not
assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.02 /Jun.99
Hyundai Semiconductor
HY62256A Series
32Kx8bit CMOS SRAM
DESCRIPTION
The HY62256A is a high-speed, low power and
32,786 x 8-bits CMOS Static Random Access
Memory
fabricated
using
Hyundai's
high
performance CMOS process technology. The
HY62256A has a data retention mode that
guarantees data to remain valid at the minimum
power supply voltage of 2.0 volt. Using the CMOS
technology, supply voltages from 2.0 to 5.5volt
has little effect on supply current in the data
retention mode. The HY62256A is suitable for use
in low voltage operation and battery back-up
application.
FEATURES
Fully static operation and Tri-state output
TTL compatible inputs and outputs
Low power consumption
Battery backup(L/LL-part)
- 2.0V(min.) data retention
Standard pin configuration
- 28 pin 600 mil PDIP
- 28 pin 330mil SOP
- 28 pin 8x13.4 mm TSOP-I
(Standard and Reversed)
Product
Voltage
Speed
Operation
Standby Current(uA)
Temperature
No.
(V)
(ns)
Current(mA)
L
LL
(
°C)
HY62256A
5.0
55/70/85
50
1mA
100
25
0~70(Normal)
Note 1. Current value is max.
PIN CONNECTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
/WE
A8
A9
A11
/OE
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
/WE
A8
A9
A11
/OE
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
/CS
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A1
A2
/OE
A11
A9
A8
A13
/WE
Vcc
A14
A12
A7
A6
A5
A4
A3
I/O8
14
13
12
11
10
9
8
7
6
5
4
3
2
1
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A2
A1
I/O1
I/O2
I/O3
Vss
I/O4
I/O5
I/O6
I/O7
I/O8
/CS
A10
A3
A4
A5
A6
A7
A12
A14
Vcc
/WE
A13
A8
A9
A11
/OE
A0
PDIP
SOP
TSOP-I(Standard)
TSOP-I(Reversed)
PIN DESCRIPTION
BLOCK DIAGRAM
Pin Name
Pin Function
/CS
Chip Select
/WE
Write Enable
/OE
Output Enable
A0 ~ A14
Address Inputs
I/O1 ~ I/O8
Data Input/Output
Vcc
Power(
+5.0V)
Vss
Ground
A14
COLUMN
DECODER
A0
ROW DECODER
MEMORY ARRAY
512x512
SENSE
AMP
OUTPUT
BUFFER
I/O1
I/O8
ADD
INPUT
BUFFER
/CS
/OE
/WE
WRITE
DRIVER
CONTROL
LOGIC
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PDF描述 |
|---|---|
| HY62256AR1-70I | x8 SRAM |
| HY62256AR1-85 | x8 SRAM |
| HY62256AR1-I55 | x8 SRAM |
| HY62256AR1-I85 | x8 SRAM |
| HY62256ASERIES | IC-256K CMOS SRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HY62256AR1-70I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| HY62256AR1-85 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| HY62256AR1-I55 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| HY62256AR1-I85 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| HY62256AR2-I | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:32Kx8bit CMOS SRAM |
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