
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.07 /Jan.99 Hyundai Semiconductor
HY62V16100-(I)/HY62U16100-(I) Series
64Kx16bit CMOS SRAM
DESCRIPTION
The HY62V16100-(I)/HY62U16100-(I) is a high-
speed, low power and 1M bits CMOS SRAM
organized as 65,536 words by 16 bits. The
HY62V16100-(I)/ HY62U16100-(I) uses sixteen
common input and output lines and has an output
enable pin which operates faster than address
access time at a read cycle. The device is
fabricated using HYUNDAI's advanced CMOS
process and designed with high-speed low power
circuit technology. It is particulary well suited for
being used in high-density and low power system
applications.
FEATURES
Fully static operation and Tri-state output
TTL compatible inputs and outputs
Data Byte Control
- LB : I/O1 ~ I/O8, UB : I/O9 ~ I/O16
Battery backup(L/LL-part)
- 2.0V(min) data retention
Standard pin configuration
- 44pin 400mil TSOP-II
(Standard and Reversed)
Product
No.
HY62V16100
HY62V16100-I
HY62U16100
HY62U16100-I
Note 1. E.T. : Extended Temperature, Normal : Normal Temperature
2. Current value is max.
Supply
Voltage(V)
3.3
3.3
3.0
3.0
Speed
(ns)
85/100/120
85/100/120
100/120/150
100/120/150
Operation
Current(mA)
5
5
5
5
Standby Current(uA)
L
50
50
50
50
Temperature.
(
°
C)
0~70(Normal)
-40~85(E.T.)
0~70(Normal)
-40~85(E.T.)
LL
10
15
10
10
PIN CONNECTION BLOCK DIAGRAM
A5
A7
IVcc
I/O5
A15
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A10
A9
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Vcc
/CS
A0
TSOP-II(Standard) TSOP-II(Reversed)
PIN DESCRIPTION
Pin Name
/CS
/WE
/OE
/LB
/UB
Pin Funtion
Pin Name
I/O1~I/O16
A0~A15
Vcc
Vss
NC
Pin Funtion
Data Input/Output
Address Input
Power(3.3V/3.0V)
Ground
No Connection
Chip Select
Write Enable
Output Enable
Low Byte Control(I/O1~I/O8)
Upper Byte Control(I/O9~I/O16)
A12
A13
ROW
DECODER
C
B
MEMORY ARRAY
512x128x16
S
W
O
B
I/O1
I/O8
I/O9
I/O16
P
A
B
A
B
A
B
A1~A7
A14
A15
A8
A9
A10
A11
A0
/CS
/OE
/LB
/UB
/WE