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參數資料
| 型號： | HYB 39S256400AT |
| 廠商： | SIEMENS AG |
| 英文描述： | 256-Mbit(4banks × 16MBit × 4) Synchronous DRAM(256M(4列 × 16M位 × 4)同步動態RAM) |
| 中文描述： | 256兆位（4banks × 16兆× 4）同步DRAM（256M（4列× 1,600位× 4）同步動態RAM）的 |
| 文件頁數： | 1/42頁 |
| 文件大小： | 282K |
| 代理商： | HYB 39S256400AT |
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HYB 39S256400/800/160AT
256-MBit Synchronous DRAM
Data Book
1
1.00
The HYB 39S256400/800/160AT are four bank Synchronous DRAM’s organized as
4 banks
×
16 MBit
×
4, 4 banks
×
8 MBit
×
8 and 4 banks
×
4 Mbit
×
16 respectively. These
synchronous devices achieve high speed data transfer rates for CAS-latencies by employing a chip
architecture that prefetches multiple bits and then synchronizes the output data to a system clock.
The chip is fabricated using the Infineon advanced 0.19
μ
m 256 MBit DRAM process technology.
The device is designed to comply with all industry standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of is
possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a
single 3.3 V
±
0.3 V power supply and are available in TSOPII packages.
High Performance:
Fully Synchronous to Positive Clock Edge
0 to 70
°
C operating temperature
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2 & 3
Programmable Wrap Sequence: Sequential
or Interleave
Programmable Burst Length: 1, 2, 4, 8
Multiple Burst Read with Single Write
Operation
Automatic and Controlled Precharge
Command
Data Mask for Read/Write Control (x4, x8)
Data Mask for Byte Control (x16)
Auto Refresh (CBR) and Self Refresh
Power Down Mode
8192 Refresh Cycles / 64 ms (7.8
μ
s)
Random Column Address every CLK
(1-N Rule)
Single 3.3 V
±
0.3 V Power Supply
LVTTL Interface
Plastic Packages:
P-TSOPII-54 400mil width (x4, x8, x16)
-7.5 version for PC133 3-3-3 application
-8 parts for PC100 2-2-2 operation
-8A parts for PC100 3-2-2 operation
-8B parts for PC100 3-2-3 operation
-7.5
-8
-8A
-8B
Units
f
CK
133
125
125
100
MHz
t
CK3
7.5
8
8
10
ns
t
AC3
5.4
6
6
6
ns
t
CK2
10
10
12
15
ns
t
AC2
6
6
6
7
ns
256-MBit Synchronous DRAM
相關PDF資料 |
PDF描述 |
|---|---|
| HYB 39S256800AT | 256-Mbit(4banks × 8MBit × 8) Synchronous DRAM(256M(4列 × 8M位 × 8)同步動態RAM) |
| HYB 39S256160AT | 256-Mbit(4banks × 4MBit × 16) Synchronous DRAM(256M(4列 × 4M位 × 16)同步動態RAM) |
| HYB 39S256400CT | 256-Mbit(4banks × 16MBit × 4) Synchronous DRAM(256M(4列 × 16M位 × 4)同步動態RAM) |
| HYB 39S256800CT | 256-Mbit(4banks × 8MBit × 8) Synchronous DRAM(256M(4列 × 8M位 × 8)同步動態RAM) |
| HYB 39S256160CT | 256-Mbit(4banks × 4MBit × 16) Synchronous DRAM(256M(4列 × 4M位 × 16)同步動態RAM) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HYB39S256400AT-7.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SDRAM |
| HYB39S256400AT-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SDRAM |
| HYB39S256400AT-8A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SDRAM |
| HYB39S256400AT-8B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SDRAM |
| HYB39S256400CT-7.5 | 制造商:Infineon Technologies AG 功能描述:64M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
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