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參數資料
| 型號： | HYB25D256400BC-8 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 256-Mbit Double Data Rate SDRAM, Die Rev. B |
| 中文描述： | 256兆雙倍數據速率SDRAM，模具版本B |
| 文件頁數： | 1/77頁 |
| 文件大小： | 1779K |
| 代理商： | HYB25D256400BC-8 |
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HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Data Sheet Jan. 2003, V1.1
2003-01-09, V1.1
Page 1 of 77
Features
CAS Latency and Frequency
Double data rate architecture: two data transfers
per clock cycle
Bidirectional data strobe (DQS) is transmitted
and received with data, to be used in capturing
data at the receiver
DQS is edge-aligned with data for reads and is
center-aligned with data for writes
Differential clock inputs (CK and CK)
Four internal banks for concurrent operation
Data mask (DM) for write data
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge;
data and data mask referenced to both edges of
DQS
Burst Lengths: 2, 4, or 8
CAS Latency: (1.5), 2, 2.5, (3)
Auto Precharge option for each burst access
Auto Refresh and Self Refresh Modes
7.8 s Maximum Average Periodic Refresh
Interval (8K refresh)
2.5V (SSTL_2 compatible) I/O
V
DDQ
= 2.5V ± 0.2V / V
DD
= 2.5V ± 0.2V
TSOP66 package
60 balls BGA w/ 3 depop rows (“chipsize pack-
age”) 12 mm x 8 mm.
Description
The 256Mb DDR SDRAM is a high-speed CMOS,
dynamic random-access memory containing 268,435,456
bits. It is internally configured as a quad-bank DRAM.
The 256Mb DDR SDRAM uses a double-data-rate archi-
tecture to achieve high-speed operation. The double data
rate architecture is essentially a
2n
prefetch architecture
with an interface designed to transfer two data words per
clock cycle at the I/O pins. A single read or write access
for the 256Mb DDR SDRAM effectively consists of a sin-
gle
2n
-bit wide, one clock cycle data transfer at the inter-
nal DRAM core and two corresponding n-bit wide, one-
half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver.
DQS is a strobe transmitted by the DDR SDRAM during
Reads and by the memory controller during Writes. DQS
is edge-aligned with data for Reads and center-aligned
with data for Writes.
The 256Mb DDR SDRAM operates from a differential
clock (CK and CK; the crossing of CK going HIGH and CK
going LOW is referred to as the positive edge of CK).
Commands (address and control signals) are registered at
every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and con-
tinue for a programmed number of locations in a pro-
grammed sequence. Accesses begin with the registration
of an Active command, which is then followed by a Read
or Write command. The address bits registered coincident
with the Active command are used to select the bank and
row to be accessed. The address bits registered coinci-
dent with the Read or Write command are used to select
the bank and the starting column location for the burst
access.
The DDR SDRAM provides for programmable Read or
Write burst lengths of 2, 4 or 8 locations. An Auto Pre-
charge function may be enabled to provide a self-timed
row precharge that is initiated at the end of the burst
access.
As with standard SDRAMs, the pipelined, multibank archi-
tecture of DDR SDRAMs allows for concurrent operation,
thereby providing high effective bandwidth by hiding row
precharge and activation time.
An auto refresh mode is provided along with a power-sav-
ing power-down mode. All inputs are compatible with the
JEDEC Standard for SSTL_2. All outputs are SSTL_2,
Class II compatible.
Note:
The functionality described and the timing specifi-
cations included in this data sheet are for the DLL Enabled
mode of operation.
CAS Latency
Maximum Operating Frequency (MHz)
DDR200
-8
-7
100
133
125
143
DDR266A
DDR266
-7F
133
143
DDR333
-6
133
166
2
2.5
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