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參數(shù)資料
| 型號(hào)： | HYB39S16320TQ-7 |
| 廠商： | SIEMENS A G |
| 元件分類： | DRAM |
| 英文描述： | 128 x 64 pixel format, LED Backlight available |
| 中文描述： | 512K X 32 SYNCHRONOUS GRAPHICS RAM, 5.5 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 1/70頁 |
| 文件大小： | 563K |
| 代理商： | HYB39S16320TQ-7 |
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Semiconductor Group
1
1998-10-01
Overview
The HYB 39S163200TQ are dual bank Synchronous Graphics DRAM’s (SGRAM) organized as
2 banks
×
256 Kbit
×
32 with built-in graphics features. These synchronous devices achieve high
speed data transfer rates up to 143 MHz by employing a chip architecture that prefetches multiple
bits and then synchronizes the output data to a system clock. The chip is fabricated with an
advanced 64MBit DRAM process technology.
The device is designed to comply with all JEDEC standards set for synchronous graphics DRAM
products, both electrically and mechanically.
RAS, CAS, WE, DSF and CS are pulsed signals which are examined at the positive edge of each
externally applied clock. Internal chip operating modes are defined by combinations of these
signals. A ten bit address bus accepts address data in the conventional RAS/CAS multiplexing
style. Ten row address bits (A0 - A9) and a bank select BA are strobed with RAS. Column address
bits plus a bank select are strobed with CAS.
Prior to any access operation, the CAS latency, burst length and burst sequence must be
programmed into the device by address inputs during a mode register set cycle. An Auto Precharge
function may be enabled to provide a self-timed row precharge. This is initiated at the end of the
burst sequence. In addition, it features the write per bit, the block write and the masked block write
High Performance:
Single Pulsed RAS Interface
Programmable CAS Latency: 2, 3
Fully Synchronous to Positive Clock Edge
Programmable Wrap Sequence:
Sequential or Interleave
Programmable Burst Length:
1, 2, 4, 8 and full page for sequential
1, 2, 4, 8 for interleave
-6
-7
-7
-8
Units
f
CK
166
125
125
125
MHz
latency
3
2
3
3
t
CK3
6
8
7
8
ns
t
AC3
5.5
5.5
5.5
6
ns
Special Mode Registers
Two color registers
Burst Read with Single Write Operation
Block Write and Write-per-Bit Capability
Byte controlled by DQM0-3
Auto Precharge and Auto Refresh Modes
Suspend Mode and Power Down Mode
2k refresh cycles/32 ms
t
AC
= 5 ns
t
SETUP
/
t
HOLD
= 2 ns/1 ns
Latency 2 @ 125 MHz
Random Column Address every CLK
(1-N Rule)
Single 3.3 V
±
0.3 V Power Supply
LVTTL compatible inputs and outputs
HYB 39S13620TQ-6/-7/-8
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB39S16320TQ-8 | 128 x 64 pixel format, LED Backlight available |
| HYB39S13620TQ- | 128 x 64 pixel format, LED Backlight available |
| HYB39S16320TQ-10 | 128 x 64 pixel format, LED Backlight available |
| HYB39S16400-1 | 16 MBit Synchronous DRAM |
| HYB39S16400CT-8 | 16 MBit Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB39S16320TQ-8 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Special Mode Registers Two color registers Burst Read with Single Write Operation |
| HYB39S1632TQ55 | 制造商:N/A 功能描述:NEW |
| HYB39S16400 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16 MBit Synchronous DRAM |
| HYB39S16400-1 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16 MBit Synchronous DRAM |
| HYB39S16400AT-10 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16 MBit Synchronous DRAM |
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