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參數(shù)資料
型號: HYS 72V64200GR
廠商: SIEMENS AG
英文描述: PC100 Registered SDRAM-Module(PC100 用于寄存的 SDRAM 模塊)
中文描述: 注冊PC100的內(nèi)存模塊(PC100的用于寄存的內(nèi)存模塊)
文件頁數(shù): 1/22頁
文件大小: 217K
代理商: HYS 72V64200GR
Data Book
1
3.00
HYS 72Vx2xxGR
PC100 Registered SDRAM-Modules
3.3 V 168-pin Registered SDRAM Modules
64 MB, 128 MB, 256 MB, 512 MB & 1 GB Densities
The HYS 72Vx2x0GR family are industry standard 168-pin 8-byte Dual in-line Memory Modules
(DIMMs) which are organized as 8M
×
72, 16M
×
72, 32M
×
72, 64M
×
72 & 128M
×
72 high speed
memory arrays designed with Synchronous DRAMs (SDRAMs) for ECC applications. The 32M x 72
(256MByte) registered DIMM module is available in two versions (12 or 13 row addresses). All
control and address signals are registered on-DIMM and the design incorporates a PLL circuit for
the Clock inputs. Use of an on-board register reduces capacitive loading on the input signals but are
delayed by one cycle in arriving at the SDRAM devices. Decoupling capacitors are mounted on the
PC board. The DIMMs use a serial presence detects scheme implemented via a serial E
2
PROM
using the 2-pin I
2
C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the
second 128 bytes are available to the end user. All Infineon 168-pin DIMMs provide a high
performance, flexible 8-byte interface in a 133.35 mm long footprint.
168-pin JEDEC Standard, Registered 8 Byte
Dual-In-Line SDRAM Module
for PC and Server main memory applications
One bank 8M
×
72, 16M
×
72, 32M
×
72 and
64M
×
72 organization,
two bank 128M
×
72 organization
Optimized for ECC applications with very low
input capacitances
Programmed Latencies:
Single + 3.3 V (
±
0.3 V) power supply
Programmable CAS Latency, Burst Length,
and Wrap Sequence (Sequential &
Interleave)
Auto Refresh (CBR) and Self Refresh
All inputs and outputs are LVTTL compatible
Serial Presence Detect with E
2
PROM
Utilizes SDRAMs in TSOPII-54 packages
with registers and PLL.
The two bank module uses stacked TSOP54
packages.
Card Size: 133.35 mm
×
38.1 mm/
43.18 mm
×
4,00/6.50 mm with Gold contact
pads
This specification follows INTEL’s “PC
SDRAM Registered DIMM Specification”
Rev. 1.2
Product Speed
CL
t
RCD
2
t
RP
2
-8
PC100
2
-8A
PC100
3
2
2
Performance:
-8
-8A
Unit
PC100
PC100
f
CK
t
CK
t
AC
Clock Frequency (max.)
100
100
MHz
Clock Cycle Time (min.)
10
10
ns
Clock Access Time (min.)
6
6
ns
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