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參數(shù)資料
| 型號： | WED2DL32512V40BI |
| 元件分類： | SRAM |
| 英文描述： | 512K X 32 MULTI DEVICE SRAM MODULE, 4 ns, PBGA119 |
| 封裝： | PLASTIC, BGA-119 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大小： | 143K |
| 代理商： | WED2DL32512V40BI |
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
WED2DL32512V
January 2000 Rev. 0
DESCRIPTION
The WEDC SyncBurst - SRAM family employs high-speed, low-
power CMOS designs that are fabricated using an advanced CMOS
process. WEDC’s 16Mb SyncBurst SRAMs integrate two 512K x 16
SRAMs into a single BGA package to provide 512K x 32 configura-
tion. All synchronous inputs pass through registers controlled by a
positive-edge-triggered single-clock input (CLK). The synchronous
inputs include all addresses, all data inputs, active LOW chip enable
(CE), burst control input (ADSC) and byte write enables (BW0-3).
Asynchronous inputs include the output enable (OE), clock (CLK)
and snooze enable (ZZ). There is also a burst mode input (MODE)
that selects between interleaved and linear burst modes. Write cycles
can be from one to four bytes wide, as controlled by the write control
inputs. Burst operation can be initiated with the address status
controller (ADSC) input.
* This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
512Kx32 Synchronous Pipeline Burst SRAM PRELIMINARY*
FEATURES
s Fast clock speed: 200, 166, 150 & 133MHz
s Fast access times: 2.5ns, 3.5ns, 3.8ns & 4.0ns
s Fast OE access times: 2.5ns, 3.5ns, 3.8ns 4.0ns
s Single +3.3V power supply (VDD)
s Separate +3.3V or +2.5V isolated output buffer supply (VDDQ)
s Snooze Mode for reduced-power standby
s Single-cycle deselect
s Common data inputs and data outputs
s Individual Byte Write control and Global Write
s Clock-controlled and registered addresses, data I/Os and control signals
s Burst control (interleaved or linear burst)
s Packaging:
119-bump BGA package
s Low capacitive bus loading
FIG. 1
BLOCK DIAGRAM
PIN CONFIGURATION
(TOP VIEW)
123
4
5
67
A
VDDQ
SA
NC
SA
VDDQ
B
NC
SA
ADSC
SA
NC
C
NC
SA
VDD
SA
NC
D
DQc
NC
VSS
NC
VSS
NC
DQb
E
DQc
VSS
CE
VSS
DQb
F
VDDQ
DQc
VSS
OE
VSS
DQb
VDDQ
G
DQc
BWc
NC
BWb
DQb
H
DQc
VSS
NC
VSS
DQb
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
DQd
VSS
CLK
VSS
DQa
L
DQd
BWd
NC
BWa
DQa
M
VDDQ
DQd
VSS
BWE
VSS
DQa
VDDQ
N
DQd
VSS
SA1
VSS
DQa
P
DQd
NC
VSS
SA0
VSS
NC
DQa
R
NC
SA
MODE
VDD
NC
SA
NC
T
NC
SA
NC
ZZ
U
VDDQ
DC
NC
VDDQ
DQb
DQa
SA
CLK
ADSC
OE
BWE
CE
MODE
ZZ
BWa
BWb
512K x 16
SSRAM
DQd
DQc
512K x 16
SSRAM
BWc
BWd
NOTE: DC = Do Not Connect
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